參數(shù)資料
| 型號： | ISLA118P50IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 72QFN |
| 產品培訓模塊： | Solutions for Test and Measurement Equipment |
| 標準包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 500M |
| 數(shù)據接口： | 串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 477mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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ISLA118P50
18
FN7565.2
July 25, 2011
The data format can also be controlled through the SPI port,
which overrides the OUTFMT pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 22.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The remaining
bits are computed as the XOR of the current bit position and the
next most significant bit. Figure 36 shows this operation.
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 37.
Mapping of the input voltage to the various data formats is
shown in Table 4.
I2E Requirements and
Restrictions
Overview
I2E is a blind and background capable algorithm, designed to
transparently eliminate interleaving artifacts. This circuitry
eliminates interleave artifacts due to offset, gain, and sample time
mismatches between unit A/Ds, and across supply voltage and
temperature variations in real-time.
Differences in the offset, gain, and sample times of
time-interleaved A/Ds create artifacts in the digital outputs. Each
of these artifacts creates a unique signature that may be
detectable in the captured samples. The I2E algorithm optimizes
performance by detecting error signatures and adjusting each
unit A/D using minimal additional power.
The I2E algorithm can be put in Active Run state via SPI. When
the I2E algorithm is in Active Run state, it detects and corrects
for offset, gain, and sample time mismatches in real time (see
Track Mode description). However, certain analog input
characteristics can obscure the estimation of these mismatches.
The I2E algorithm is capable of detecting these obscuring analog
input characteristics, and as long as they are present I2E will stop
updating the correction in real time. Effectively, this freezes the
current correction circuitry to the last known-good state (see Hold
Mode description). Once the analog input signal stops obscuring
the interleaved artifacts, the I2E algorithm will automatically
start correcting for mismatch in real time again.
Active Run State
During the Active Run state the I2E algorithm actively suppresses
artifacts due to interleaving based on statistics in the digitized
data. I2E has two modes of operation in this state (described
below), dynamically chosen in real-time by the algorithm based
on the statistics of the analog input signal.
Track Mode refers to the default state of the algorithm, when all
artifacts due to interleaving are actively being eliminated. To be
in Track Mode the analog input signal to the device must adhere
to the following requirements:
Posses total power greater than -20dBFS, integrated from
1MHz to Nyquist but excluding signal energy in a 100kHz band
centered at fS/4
FIGURE 36. BINARY TO GRAY CODE CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
FIGURE 37. GRAY CODE TO BINARY CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
TABLE 4. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale
000 00 000 00 00 100 00 000 00 00 000 00 000 00 00
–Full Scale + 1LSB 000 00 000 00 01 100 00 000 00 01 000 00 000 00 01
Mid–Scale
100 00 000 00 00 000 00 000 00 00 110 00 000 00 00
+Full Scale – 1LSB 111 11 111 11 10 011 11 111 11 10 100 00 000 00 01
+Full Scale
111 11 111 11 11 011 11 111 111 1 100 00 000 00 00
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