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| 型號： | ISLA118P50IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 72QFN |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Test and Measurement Equipment |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 477mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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ISLA118P50
24
FN7565.2
July 25, 2011
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 17). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
ADDRESS 0X30: I2E STATUS
The I2E general status register.
Bits 0 and 1 indicate if the I2E circuitry is in Active Run or Hold
state. The state of the I2E circuitry is dependent on the analog
input signal itself. If the input signal obscures the interleave
mismatched artifacts such that I2E cannot estimate the
mismatch, the algorithm will dynamically enter the Hold state.
For example, a DC mid-scale input to the A/D does not contain
sufficient information to estimate the gain and sample time
skew mismatches, and thus the I2E algorithm will enter the Hold
state. In the Hold state, the analog adjustments for interleave
correction will be frozen and mismatch estimate calculations will
cease until such time as the analog input achieves sufficient
quality to allow the I2E algorithm to make mismatch estimates
again.
Bit 0: 0 = I2E has not detected a low power condition. 1 = I2E has
detected a low power condition, and the analog adjustments for
interleave correction are frozen.
Bit 1: 0 = I2E has not detected a low AC power condition. 1 = I2E
has detected a low AC power condition, and I2E will continue to
correct with best known information but will not update its
interleave correction adjustments until the input signal achieves
sufficient AC RMS power.
Bit 2: When first started, the I2E algorithm can take a significant
amount of time to settle (~1s), dependent on the characteristics
of the analog input signal. 0 = I2E is still settling, 1 = I2E has
completed settling.
ADDRESS 0X31: I2E CONTROL
The I2E general control register. This register can be written while
I2E is running to control various parameters.
Bit 0: 0 = turn I2E off, 1= turn I2E on
Bit 1: 0 = no action, 1 = freeze I2E, leaving all settings in the
current state. Subsequently writing a 0 to this bit will allow I2E to
continue from the state it was left in.
Bit 2-4: Disable any of the interleave adjustments of offset, gain,
or sample time skew.
Bit 5: 0 = bypass notch filter, 1 = use notch filter on incoming
data before estimating interleave mismatch terms.
ADDRESS 0X32: I2E STATIC CONTROL
The I2E general static control register. This register must be
written prior to turning I2E on for the settings to take effect.
Bit 1-4: Reserved, always set to 0
Bit 5: 0 = normal operation, 1 = skip coarse adjustment of the
offset, gain, and sample time skew analog controls when I2E is
first turned on. This bit would typically be used if optimal analog
adjustment values for offset, gain, and sample time skew have
been preloaded in order to have the I2E algorithm converge more
quickly.
The system gain of the pair of interleaved core A/Ds can be set
by programming the medium and fine gain of the reference A/D
before turning I2E on. In this case, I2E will adjust the non-
reference A/D’s gain to match the reference A/D’s gain.
Bit 7: Reserved, always set to 0
ADDRESS 0X4A: I2E POWER DOWN
This register provides the capability to completely power down
the I2E algorithm and the Notch filter. This would typically be
done to conserve power.
BIT 0: Power down the I2E Algorithm
BIT 1: Power down the Notch Filter
ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS
This group of registers provides programming access to configure
I2E’s dynamic freeze control. As with any interleave mismatch
correction algorithm making estimates of the interleave
mismatch errors using the digitized application input signal,
there are certain characteristics of the input signal that can
obscure the mismatch estimates. For example, a DC input to the
A/D contains no information about the sample time skew
mismatch between the core A/Ds, and thus should not be used
TABLE 7. COARSE GAIN ADJUSTMENT
0x22[3:0]
NOMINAL COARSE GAIN ADJUST
(%)
Bit 3
+2.8
Bit 2
+1.4
Bit 1
-2.8
Bit 0
-1.4
TABLE 8. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
TABLE 9. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
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