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參數(shù)資料
| 型號： | IDT72T6360L6BB |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 49/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW-CTRL 36BIT 6NS 324-BGA |
| 標準包裝： | 1 |
| 類型： | 連續(xù)流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA |
| 供應商設備封裝： | 324-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T6360L6BB |
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7
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
READ PORT INTERFACE
ASYR(1)
V6
Asynchronous
INPUT
A HIGH on this input during master reset will select synchronous read operation for the
Read Port
3.3V or
output port. A LOW will select asynchronous operation. If asynchronous is selected the
2.5V LVTTL device must operate in IDT Standard mode and the read enable must be tied to GND.
EF/OR
V13
Empty Flag/
OUTPUT
In IDT Standard mode, the
EF function is selected. EF indicates whether or not the device
Output Ready
3.3V or
memory is empty. In FWFT mode, the
OR function is selected. OR indicates whether or not
2.5V LVTTL there is valid data available at the outputs.
OE
U12
OutputEnable
INPUT
Asynchronous three-state control of the data outputs. All data outputs Q[35:0] will be placed
3.3V or
in high-impedance if this pin is HIGH. Conversely, all data outputs will be active when this
2.5V LVTTL pin is LOW.
PAE
U13
Programmable
OUTPUT
This is the programmable almost empty flag that can be used as an early indicator for the
AlmostEmptyFlag
3.3V or
empty boundary condition of the internal memory.
PAE goes LOW if the number of words
2.5V LVTTL in the sequential flow-control device is less than offset n, which is stored in the empty offset
register.
PAE goes HIGH if the number of words in the sequential flow-control device is
greater than or equal to the offset n.
Q[35:0]
See Pin
Data Output Bus
OUTPUT
Data outputs for a 36, 18, and 9-bit bus.
No. table
3.3V or
2.5V LVTTL
RCLK/
V9
Read Clock/
INPUT
This is a dual function pin. If synchronous operation of the read port is selected, the rising
RD
Read Strobe
3.3V or
edge of RCLK reads data from the sequential flow-control device when
REN is enabled.
2.5V LVTTL If asynchronous operation of the read port is selected, a rising edge on RD reads data
from the sequential flow-control device without the need of a free-running input read clock.
RCS
V12
Read Chip Select
INPUT
Synchronous three-state control of the data outputs. Provides another means of controlling
3.3V or
the data outputs synchronous to RCLK. Can be regarded as a second output enable
2.5V LVTTL signal.
REN
V10
Read Enable
INPUT
REN enables RCLK for reading data from the sequential flow-control device. If
3.3V or
asynchronous mode is selected on the read port, this signal should be tied to GND.
2.5V LVTTL
SREN
V11
Serial Read Enable
INPUT
When
SREN is brought LOW before the rising edge of SCLK, the contents of the PAE and
3.3V or
PAF offset registers are copied to a serial shift register. While SREN is maintained LOW, on
2.5V LVTTL each rising edge of SCLK, one bit of data is shifted out of this serial shift register through the
SO output pin used only when JSEL = 0.
WRITE PORT INTERFACE
ASYW(1)
T6
Asynchronous
INPUT
A HIGH on this input during master reset will select synchronous write operation for the
WritePort
3.3V or
input port. A LOW will select asynchronous operation. If asynchronous is selected the
2.5V LVTTL device must operate in IDT Standard mode and the write enable must be tied to GND.
D[35:0]
See Pin
DataInputs
INPUT
Data inputs for a 36, 18, and 9-bit bus.
No. table
3.3V or
2.5V LVTTL
FF/IR
R12
Full Flag/
OUTPUT
In IDT Standard mode, the
FF function is selected. FF indicates whether or not the device
Input Ready
3.3V or
memory is full. In FWFT mode, the
IR function is selected. IR indicates whether or not there
2.5V LVTTL is space available for writing to the device memory.
PAF
T12
Programmable
OUTPUT
This is the programmable almost full flag that can be used as an early indicator for the full
Almost Full Flag
3.3V or
boundary condition of the internal memory.
PAF goes HIGH if the number of free locations
2.5V LVTTL in the sequential flow-control device is more than offset m, which is stored in the full offset
register.
PAFgoes LOW if the number of free locations in the sequential flow-control device
is less than or equal to the offset m.
SWEN
T11
Serial Write Enable
INPUT
On each rising edge of SCLK when
SWEN is LOW, data from the SI pin is serially loaded
3.3V or
into the
PAE and PAF registers used only when JSEL = 0.
2.5V LVTTL
PIN DESCRIPTIONS
Symbol
Pin No.
Name
I/O TYPE
Description
Location
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| IDT72T6360L6BBG | 功能描述:IC FLOW-CTRL 36BIT 6NS 324-BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6360L7-5BB | 功能描述:IC FLOW-CTRL 48BIT 7-5NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6360L7-5BBI | 功能描述:IC FLOW-CTRL 48BIT 7-5NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6480L10BB | 功能描述:IC FLOW-CTRL 48BIT 10NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6480L10BBI | 功能描述:IC FLOW-CTRL 48BIT 10NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
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