參數(shù)資料
型號: HYB18T512800AF-3.7
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 60/117頁
文件大?。?/td> 2102K
代理商: HYB18T512800AF-3.7
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
60
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
Figure 43
Read Operation Followed by Precharge Example 4
PERLA
RL = 6, (AL = 2, CL = 4), BL = 4,
t
RTP
2 CKs
Figure 44
Read Operation Followed by Precharge Example 5
RL = 4, (AL = 0, CL = 4), BL = 8,
t
RTP
>
2 CKs
3.22.2
Write followed by Precharge
Minimum Write to Precharge command spacing to the
same bank = WL + BL/2 +
t
WR
. For write cycles, a delay
must be satisfied from the completion of the last burst
write cycle until the Precharge command can be
issued. This delay is known as a write recovery time
(
t
WR
) referenced from the completion of the burst write
to the Precharge command. No Precharge command
should be issued prior to the
t
WR
delay, as DDR2
SDRAM does not support any burst interrupt by a
Precharge command.
t
WR
is an analog timing
parameter (see
Chapter 7
) and is not the programmed
value WR in the MR.
NOP
NOP
NOP
READ A
Posted CAS
T0
T2
T1
T3
T4
T5
T6
T7
T8
CMD
DQ
BR-P624
NOP
AL + BL/2 clocks
Dout A0
Dout A1
Dout A2
Dout A3
AL = 2
CL = 4
RL = 6
>=tRAS
CL = 4
tRP
Precharge
A
Bank A
Activate
DQS,
DQS
NOP
NOP
>=tRC
>=tRTP
CK, CK
NOP
NOP
NOP
READ A
T0
T2
T1
T3
T4
T5
T6
T7
T8
CMD
DQ
BR-P404(8)
NOP
AL + BL/2 clks + 1
Dout A0
Dout A1
Dout A2
Dout A3
CL = 4
RL = 4
>=tRAS
tRP
DQS,
DQS
NOP
>=tRTP
Dout A4
Dout A5
Dout A6
Dout A7
Precharge
NOP
Bank A
Activate
first 4-bit prefetch
second 4-bit prefetch
CK, CK
相關(guān)PDF資料
PDF描述
HYB18T512800AF-3S 512-Mbit DDR2 SDRAM
HYB18T512800AC-37 M39012 MIL RF CONNECTOR
HYB18T512800AC-5 M39012 MIL RF CONNECTOR
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HYB18T512800AF DDR2 Registered Memory Modules
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