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參數(shù)資料
| 型號： | HYB18T512800AF-3.7 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁數(shù)： | 28/117頁 |
| 文件大?。?/td> | 2102K |
| 代理商： | HYB18T512800AF-3.7 |
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
28
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
3.2
Basic Functionality
Read and write accesses to the DDR2 SDRAM are
burst oriented; accesses start at a selected location
and continue for the burst length of four or eight in a
programmed sequence.
Accesses begin with the registration of an Activate
command, which is followed by a Read or Write
command. The address bits registered coincident with
the activate command are used to select the bank and
row to be accessed.
The address bits registered coincident with the Read or
Write command are used to select the starting column
location for the burst access and to determine if the
Auto-Precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register
definition, command description and device operation.
3.3
Power On and Initialization
DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below
0.2
×
V
DDQ
and ODT at a low state (all other inputs
may be undefined). To guarantee ODT off,
V
REF
must be valid and a low level must be applied to the
ODT pin. Maximum power up interval for
V
DD
/
V
DDQ
is specified as 20.0 ms. The power interval is
defined as the amount of time it takes for
V
DD
/
V
DDQ
to power-up from 0 V to 1.8 V
±
100 mV. At least
one of these two sets of conditions must be met:
–
V
DD
,
V
DDL
and
V
DDQ
are driven from a single power
converter output, AND
–
V
TT
is limited to 0.95 V max, AND
–
V
REF
tracks
V
DDQ
/2
or
– Apply
V
DD
before or at the same time as
V
DDL.
– Apply
V
DDL
before or at the same time as
V
DDQ.
– Apply
V
DDQ
before or at the same time as
V
TT
&
V
REF
.
2. Start clock (CK, CK) and maintain stable power and
clock condition for a minimum of 200
μ
s.
3. Apply NOP or Deselect commands and take CKE
high.
4. Continue NOP or Deselect Commands for 400 ns,
then issue a Precharge All command.
5. Issue EMRS(2) command.
6. Issue EMRS(3) command.
7. Issue EMRS(1) command to enable DLL.
8. Issue a MRS command for “DLL reset”.
9. Issue Precharge-all command.
10.Issue 2 or more Auto-refresh commands.
11.Issue the final MRS command to turn the DLL on
and to set the necessary operating parameter.
12.At least 200 clocks after step 8, issue EMRS(1)
commands to either execute the OCD calibration or
select the OCD default. Issue the final EMRS(1)
command to exit OCD calibration mode and set the
necessary operating parameters.
13.The DDR2 SDRAM is now ready for normal
operation.
Figure 8
Initialization Sequence after Power up
1st Auto
refresh
CK, CK
MRS
PRE
ALL
EMRS(3)
tRP
tMRS
tMRS
CKE
400 ns
NOP
ODT "low"
EMRS(2)
tMRS
EMRS(1)
tMRS
PRE
ALL
tRP
tRFC
2nd Auto
refresh
tRFC
Extended
Mode
Register(1) Set
with DLL enable
Mode
Register
Set with
DLL reset
min. 200 cycles to lock the DLL
MRS
tMRS
Follow OCD
flowchart
EMRS(1)
OCD
EMRS(1)
OCD
Any
Command
OCD Drive(1)
or
OCD default
OCD
calibration
mode exit
Mode
Register
Set w/o
DLL reset
tMRS
相關(guān)PDF資料 |
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| HYB18T512800AF-3S | 512-Mbit DDR2 SDRAM |
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| HYB18T512800AC-5 | M39012 MIL RF CONNECTOR |
| HYB18T512800AC | DDR2 Registered Memory Modules |
| HYB18T512800AF | DDR2 Registered Memory Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T512800AF-3S | 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T512800BF-3.7 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
| HYB18T512800BF-3S | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| HYB25D128160AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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