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參數(shù)資料
| 型號： | HYB18T512400AF-3S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁數(shù)： | 68/117頁 |
| 文件大小： | 2102K |
| 代理商： | HYB18T512400AF-3S |
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
68
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
Figure 53
Auto Refresh Timing
3.24.2
Self-Refresh Command
The Self-Refresh command can be used to retain data,
even if the rest of the system is powered down. When
in the Self-Refresh mode, the DDR2 SDRAM retains
data without external clocking. The DDR2 SDRAM
device has a built-in timer to accommodate Self-
Refresh operation. The Self-Refresh Command is
defined by having CS, RAS, CAS and CKE held LOW
with WE HIGH at the rising edge of the clock. The
device must be in idle state and ODT must be turned off
before issuing Self Refresh command, by either driving
ODT pin LOW or using EMRS(1) command. Once the
command is registered, CKE must be held LOW to
keep the device in Self-Refresh mode. The DLL is
automatically disabled upon entering Self Refresh and
is automatically enabled upon exiting Self Refresh.
When the DDR2 SDRAM has entered Self-Refresh
mode all of the external control signals, except CKE,
are “don’t care”. The DRAM initiates a minimum of one
Auto Refresh command internally within
t
CKE
period
once it enters Self Refresh mode. The clock is internally
disabled during Self-Refresh Operation to save power.
The minimum time that the DDR2 SDRAM must remain
in Self Refresh mode is
t
CKE
. The user may change the
external clock frequency or halt the external clock one
clock after Self-Refresh entry is registered, however,
the clock must be restarted and stable before the
device can exit Self-Refresh operation.
The procedure for exiting Self Refresh requires a
sequence of commands. First, the clock must be stable
prior to CKE going back HIGH. Once Self-Refresh Exit
command is registered, a delay of at least
t
XSNR
must
be satisfied before a valid command can be issued to
the device to allow for any internal refresh in progress.
CKE must remain HIGH for the entire Self-Refresh exit
period
t
XSRD
for proper operation. Upon exit from Self
Refresh, the DDR2 SDRAM can be put back into Self
Refresh mode after
t
XSNR
expires. NOP or deselect
commands must be registered on each positive clock
edge during the Self-Refresh exit interval
t
XSNR
. ODT
should be turned off during
t
XSNR
.
The use of Self Refresh mode introduces the possibility
that an internally timed refresh event can be missed
when CKE is raised for exit from Self Refresh mode.
Upon exit from Self Refresh, the DDR2 SDRAM
requires a minimum of one extra auto refresh command
before it is put back into Self Refresh Mode.
T0
T2
T1
T3
AR
CK, CK
CMD
Precharge
> = t
RP
NOP
AUTO
REFRESH
ANY
NOP
> = t
RFC
> = t
RFC
AUTO
REFRESH
NOP
NOP
NOP
CKE
"high"
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
| HYB18T512400BF-3S | 制造商:Qimonda 功能描述: |
| HYB18T512800AF-3S | 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T512800BF-3.7 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
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