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參數(shù)資料
| 型號： | HYB18RL25616AC-3.3 |
| 英文描述： | ?256M (16Mx16) 300MHz ? |
| 中文描述： | ？256M（16Mx16顯示）300MHz的？ |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 869K |
| 代理商： | HYB18RL25616AC-3.3 |
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HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 22
Infineon Technologies
This specification is preliminary and subject to change without notice
2.6
Reads (RD)
2.6.1
Read accesses are initiated with a READ command, as shown in
Figure 19. Row and bank addresses are provided with the READ
command.
During READ bursts the memory device drives the read data edge
aligned with the DQS signal. After a programmable read latency, data
is available at the outputs. The data valid signal indicates that valid
read data will be present on the bus after 0.5clock cycles.
The skew between DQS and CK is specified as tCKDQS.
tDQSQ is the skew between DQS edge and the last valid data edge.
tDQSQ is derived at each DQS clock edge and is not cumulative over
time.
After completion of a burst, assuming no other commands have been
initiated, output data will go High-Z. Back to back READ commands are
possible, producing a continuous flow of output data.
The data valid window is derived for each DQS transition and is defined
as: min(tDQSH, tDQSL) - 2* tQSQmax.
Any READ burst may be followed by a subsequent WRITE command.
Figure 23 shows the corresponding timing requirements for a READ
followed by a WRITE. A READ to WRITE delay has to be buit in in order
to prevent bus contention. Some systems having long line lengths or
severe skews may need additional idle cycles inserted.
Read - Basic Information
Figure 20 Basic Read Burst Timing
CK#
CK
WE#
CS#
REF#
BA<2:0>
A
BA
A:
BA:
Address
Bank Address
Don't Care
A<19:0>
AS#
Figure 19
READ command
D0
D1
D2
D3
t
CKH
t
CKL
t
CKDQS
t
CK
Don't Care
t
QSQ
t
QSQ
data
valid
window
DQS
DQS#
DVLD
DQ
t
QSVLD
t
QSVLD
CK#
CK
t
DQSL
t
DQSH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18RL25616AC-4 | ?256M (16Mx16) 250MHz ? |
| HYB18RL25616AC-5 | ?256M (16Mx16) 200MHz ? |
| HYB18RL25632AC-3.3 | ?256M (8Mx32) 300MHz ? |
| HYB18RL25632AC-5 | ?256M (8Mx32) 200MHz ? |
| HYB25D128400AT-7 | ?128Mb (32Mx4) DDR266A (2-3-3)? |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T1G400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 256M x 4, 68 Pin, Plastic, BGA |
| HYB18T1G400AF-5 | 制造商:Infineon Technologies AG 功能描述:256M X 4 DDR DRAM, 0.6 ns, PBGA68 |
| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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