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參數(shù)資料
| 型號： | HYB18RL25616AC-3.3 |
| 英文描述： | ?256M (16Mx16) 300MHz ? |
| 中文描述： | ？256M（16Mx16顯示）300MHz的？ |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 869K |
| 代理商： | HYB18RL25616AC-3.3 |
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HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 15
Infineon Technologies
This specification is preliminary and subject to change without notice
2.2
Initialization
The RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation or permanent damage to the device.
The following sequence is used for Power-Up:
1.Apply power (VEXT, VDD, VDDQ, VREF) and start clock as soon as the supply voltages are stable. Apply
VDD and VEXT before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF.
There is no timing relation between VEXT and VDD, the chip starts the power up sequence only when
both voltages are at their nominal level. However, the pad supply must not be applied before the core
supplies. Maintain all pins in NOP conditions.
2.Maintain stable conditions for 200 s minimum.
3.Issue three Mode Register Set commands - 2 dummies plus 1 valid MRS (Figure 7).
4.After tMRSC issue 8 Auto Refresh commands, one on each bank and separated by 2048 cycles.
5.After tRC the chip is ready for normal operation.
Figure 7
Power Up Sequence
Note: When the RLDRAM is powered up with the matched impedance mode inactive, the 2048 cycles between the 8 Refresh
commands are not required . These cycles are necessary in order to calibrate the Output drivers.
Don't Care
MRS:
RF:
MRS command
REFRESH
A.C.:
Any command
CK
MRS
t
MRSC
MRS
MRS
min. 200 μs
Com.
VDD
VDDQ
VREF
CK#
VEXT
min. 2048
cycles
RF
A.C.
RF
RF
6 x 2048
cycles
t
RC
Add
BA0
BA1
BA7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18RL25616AC-4 | ?256M (16Mx16) 250MHz ? |
| HYB18RL25616AC-5 | ?256M (16Mx16) 200MHz ? |
| HYB18RL25632AC-3.3 | ?256M (8Mx32) 300MHz ? |
| HYB18RL25632AC-5 | ?256M (8Mx32) 200MHz ? |
| HYB25D128400AT-7 | ?128Mb (32Mx4) DDR266A (2-3-3)? |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T1G400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 256M x 4, 68 Pin, Plastic, BGA |
| HYB18T1G400AF-5 | 制造商:Infineon Technologies AG 功能描述:256M X 4 DDR DRAM, 0.6 ns, PBGA68 |
| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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