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參數(shù)資料
| 型號： | HYB18RL25616AC-3.3 |
| 英文描述： | ?256M (16Mx16) 300MHz ? |
| 中文描述： | ？256M（16Mx16顯示）300MHz的？ |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 869K |
| 代理商： | HYB18RL25616AC-3.3 |
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HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 13
Infineon Technologies
This specification is preliminary and subject to change without notice
1.5.2
Description of Commands
Table 5
Description of Commands
Note: 1: Actual refresh is 32ms/8K/8 = 0.488μs
Note: 2: Actual refresh is 32ms/8K = 3.90μs
Command Description
DESEL /
NOP
The NOP command is used to perform a no operation to the RLDRAM; this is equal to deselecting
the chip. Use NOP command to prevent unwanted commands from being registered during idle
or wait states. Operations already in progress are not affected. Output values depend on
command history.
The Mode Register is set via the address inputs A[17:0]. See the mode register description in the
register description section. The MRS command can only be issued when all banks are idle and
no bursts are in progress.
The READ command is used to initiate a burst read access to a bank. The value on the BA[2:0]
inputs selects the bank, and the address provided on inputs A[19:0] selects the data location
within the bank.
The WR command is used to initiate a burst write access to a bank. The value on the BA[2:0]
inputs selects the bank, and the address provided on inputs A[19:0] selects the data location
within the bank. Input data appearing on the DQs is written to the memory array subject to the
DMx input logic levels appearing coincident with the WRITE command. If DM0 is registered LOW,
the first half of the burst Write data will be written to the memory array, if registerd HIGH this data
will be ignored i.e, this part of the data word will not be written. If DM1 is registered LOW the
second half of the burst Write data will be written to the memory array, if registerd HIGH this data
will be ignored i.e, this part of the data word will not be written.
The AREF is used during normal operation of the RLDRAM to refresh the memory content of a
bank. The value on the BA[2:0] inputs selects the bank. The refresh address is generated by the
internal refresh controller. This makes the address bits “Don’t Care” during an AREF command.
The RLDRAM requires 64k AREF cycles at an average periodic interval of 0.49 μs
1)
(maximum).
To improve efficiency a burst of eight AREF commands (One AREF for each bank) can be posted
to the RLDRAM at an average periodic interval of 3.9μs
2)
.
MRS
READ
WRITE
AREF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18RL25616AC-4 | ?256M (16Mx16) 250MHz ? |
| HYB18RL25616AC-5 | ?256M (16Mx16) 200MHz ? |
| HYB18RL25632AC-3.3 | ?256M (8Mx32) 300MHz ? |
| HYB18RL25632AC-5 | ?256M (8Mx32) 200MHz ? |
| HYB25D128400AT-7 | ?128Mb (32Mx4) DDR266A (2-3-3)? |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T1G400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 256M x 4, 68 Pin, Plastic, BGA |
| HYB18T1G400AF-5 | 制造商:Infineon Technologies AG 功能描述:256M X 4 DDR DRAM, 0.6 ns, PBGA68 |
| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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