參數(shù)資料
型號(hào): HYB18RL25616AC-3.3
英文描述: ?256M (16Mx16) 300MHz ?
中文描述: ?256M(16Mx16顯示)300MHz的?
文件頁(yè)數(shù): 12/36頁(yè)
文件大?。?/td> 869K
代理商: HYB18RL25616AC-3.3
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 12
Infineon Technologies
This specification is preliminary and subject to change without notice
1.5
Commands
1.5.1
According to the functional signal description the following command sequences are possible. All input
states or sequences not shown are illegal or reserved. All command and address inputs must meet setup
and hold times around the rising edge of CK.
Command Table
Table 3
Truth table
Note: 1: X = “Don’t Care” ; H = Logic HIGH; L = Logic LOW
Note: 2: Only A[17:0] are used for the MRS command.
Note: 3: See Table 4
Table 4
Address Width table
Data Width
Burst Length
BL 2
BL 4
Note: 1: The x32 and x16 configurations have different ballouts (see Fig. 2 & Fig. 3)
Operation
Device
State
Any
Any
Idle
Any
Any
Idle
Code
CS#
AS#
WE#
REF#
A[19:0]
1)3)
BA]2:0]
DM]1:0]
No Operation
Deselect
4)
Mode Register Set
2)
Read
Write
Auto Refresh
NOP
L
H
L
L
L
L
H
X
L
L
L
H
H
X
L
H
L
H
H
X
L
H
H
L
X
X
X
X
X
X
X
X
X
MRS
READ
WRITE
Valid
Valid
Valid
X
Valid
Valid
Valid
Valid
X
32
16
A[18:0]
A[17:0]
A[19:0]
A[18:0]
相關(guān)PDF資料
PDF描述
HYB18RL25616AC-4 ?256M (16Mx16) 250MHz ?
HYB18RL25616AC-5 ?256M (16Mx16) 200MHz ?
HYB18RL25632AC-3.3 ?256M (8Mx32) 300MHz ?
HYB18RL25632AC-5 ?256M (8Mx32) 200MHz ?
HYB25D128400AT-7 ?128Mb (32Mx4) DDR266A (2-3-3)?
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