參數(shù)資料
型號(hào): HYB18RL25616AC-3.3
英文描述: ?256M (16Mx16) 300MHz ?
中文描述: ?256M(16Mx16顯示)300MHz的?
文件頁數(shù): 11/36頁
文件大?。?/td> 869K
代理商: HYB18RL25616AC-3.3
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 11
Infineon Technologies
This specification is preliminary and subject to change without notice
Figure 5
Functional Block Diagram 16M x 16 Configuration
Note: 1 When the BL4 setting is used, A19 is a "Don’t Care".
Note: 2 In the 16Mx16 configuration, only DQS[1:0] & DQS#[1:0] are used
A0-A19, B0, B1, B2
Column Address
Counter
Column Address Buffer
Row Address Buffer
Refresh Counter
Input Buffers
Row Decoder
Memory Array
Bank 0
S
C
Row Decoder
Memory Array
Bank 1
S
C
Row Decoder
Memory Array
Bank 2
S
C
Row Decoder
Memory Array
Bank 3
S
C
Row Decoder
Memory Array
Bank 7
S
C
Row Decoder
Memory Array
Bank 6
S
C
Row Decoder
Memory Array
Bank 5
S
C
Row Decoder
Memory Array
Bank 4
S
C
Output Buffers
Data read strobe
Output Data Valid
Control Logic and Timing Generators
DVLD
DQS[1:0], DQS#[1:0]
DQ0-DQ15
C
C
A
D
W
C
R
D
V
相關(guān)PDF資料
PDF描述
HYB18RL25616AC-4 ?256M (16Mx16) 250MHz ?
HYB18RL25616AC-5 ?256M (16Mx16) 200MHz ?
HYB18RL25632AC-3.3 ?256M (8Mx32) 300MHz ?
HYB18RL25632AC-5 ?256M (8Mx32) 200MHz ?
HYB25D128400AT-7 ?128Mb (32Mx4) DDR266A (2-3-3)?
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