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參數(shù)資料
| 型號： | HTG2190 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit 1024 Pixel LCD Microcontroller |
| 中文描述： | 8位單片機(jī)1024像素LCD |
| 文件頁數(shù)： | 34/64頁 |
| 文件大?。?/td> | 417K |
| 代理商： | HTG2190 |
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HTG2190
Rev. 1.00
34
June 29, 2001
After a chip reset, these input/output lines stay
at Schmitt trigger input with pull-high resistor.
Eachbitoftheseinput/outputlatchescanbeset
or cleared by the SET [m].i or CLR [m].i
(m=12H, 14H, 16H, 18H, 1AH) instruction.
Some instructions first input data and then fol-
low the output operations. For example, the
SET [m].i, CLR [m].i, CPL [m] and CPLA [m]
instructions read the entire port states into the
CPU, execute the defined operations
(bit-operation), and then write the results back
to the latches or the accumulator.
Each line of port A has a wake-up capability. PC,
PD and PE can be selected as segment output by
mask option. If the segment output is selected,
the related I/O register (PC, PD and PE) cannot
be used as a general purpose register. Reading
the register will result to an unknown state.
PWM interface
The HTG2190 provides an 8 bit (bit7 is a sign
bit) PWM D/A interface, which is good for
speech synthesis. The user can record or syn-
thesize the sound and digitize it into the pro-
gram ROM.
These sound could be played back in sequence
of the function as designed by the internal pro-
gram ROM. There are several algorithms that
can be used in the HTG2190, they are PCM,
LAW, DPCM, ADPCM.....
The PWM circuit provides two pad outputs:
PWM2, PWM1 which can directly drive a piezo
or a 32
speaker without adding any external
element. Refer to the Application Circuits.
The PWM clock source comes from the system
clock divided by a 3-bit prescaler. Setting data
to P0, P1 and P2 (bit 3, 4, 5 of 27H) can generate
various clock sources. The clock source are used
for PWM modulating clock and sampling clock.
After setting the start bit (bit 0 of 27H) and the
next falling edge coming from the prescaler, the
DIV will generate a serial clock to PWM coun-
terformodulationandPWMIforinterrupt.The
PWM counter latch data at the first F1 clock
falling edge and the start counter at F1 rising
edge. The PWM base frequency is 32kHz. For
every 32kHz latch data once. The F2 clock is
synchronous with the first F1 clock and it is
also connected to the PWM output latch. In set-
ting the start bit
initial status, the PWM1
DAC outputs a low level and change the out-
put status to high while the 7-bit counter
overflows.
BZ/SP
6/7
Bit
F1
F2
(Sampling
Rate)
Device
0
0
F0
F0/64
32
speaker
0
1
F0
F0/128
32
speaker
1
0
F0
F0/64
Buzzer/8
speaker
1
1
F0
F0/128
Buzzer/8
speaker
Note: "F1" for PWM modulation clock and F2
for sampling clock
"F0" f
SYS
/(n+1) n=0~7 (n:3 bits preload
counter)
9
,
&
9
9 .
& -
. 3 & -@
" #
4 . @ : ;
7 bits PWM counter bit
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