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參數(shù)資料
| 型號： | HTG2190 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit 1024 Pixel LCD Microcontroller |
| 中文描述： | 8位單片機(jī)1024像素LCD |
| 文件頁數(shù)： | 20/64頁 |
| 文件大?。?/td> | 417K |
| 代理商： | HTG2190 |
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HTG2190
Rev. 1.00
20
June 29, 2001
Status register
STATUS
This 8-bit register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD) and
Watchdog time-out flag (TO). It also records the
status information and controls the operation se-
quence.
With the exception of the TO and PD flags, bits
in the status register can be altered by instruc-
tions like any other register. Any data written
into the status register will not change the TO
or PD flags. In addition, operations related to
the status register may give different results
from those intended. The TO and PD flags can
only be changed by a system power up,
Watchdog Timer overflow, executing the HALT
instruction and clearing the Watchdog Timer.
The Z, OV, AC and C flags generally reflect the
status of the latest operations.
In addition, on entering the interrupt sequence
or executing the subroutine call, the status reg-
ister will not be pushed onto the stack automat-
ically. If the contents of the status register are
important and the subroutine can corrupt the
status register, the programmer must take pre-
cautions to save it properly.
Interrupt
The HTG2190 provides external and a PWM
D/A interrupt and internal timer/event counter
interrupts. The interrupt control register
(INTC;0BH, INTCH;1EH) contains the interrupt
control bits to set the enable/disable and the in-
terrupt request flags.
Once an interrupt subroutine is serviced, all
other interrupts will be blocked (by clearing the
EMI bit). This scheme may prevent any further
interrupt nesting. Other interrupt requests may
happen during this interval but only the inter-
rupt request flag is recorded. If a certain inter-
rupt needs servicing within the service routine,
the EMI bit and the corresponding INTC bit
may be set to allow interrupt nesting. If the
stack is full, the interrupt request will not be ac-
knowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate
service is desired, the stack must be prevented
from becoming full.
All these kinds of interrupt have the wake-up
capability. As an interrupt is serviced, a control
transferoccursbypushingtheprogramcounter
and A15~A13 bits onto the stack and then
branching to subroutines at specified loca-
Labels Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a bor-
row does not take place during a subtraction operation; otherwise C is cleared. Also
it is affected by a rotate through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a carry
out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared when either a system power-up or executing the CLR WDT instruc-
tion. PD is set by executing the HALT instruction.
TO
5
TO is cleared by a system power-up or executing the CLR WDT or HALT instruc-
tion. TO is set by a WDT time-out.
6,7
Unused bit, read as "0"
STATUS register
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