參數(shù)資料
型號(hào)： HTG2190
廠商： Holtek Semiconductor Inc.
元件分類(lèi)： 8位微控制器
英文描述： 8-Bit 1024 Pixel LCD Microcontroller
中文描述： 8位單片機(jī)1024像素LCD
文件頁(yè)數(shù)： 21/64頁(yè)
文件大?。?/td> 417K
代理商： HTG2190
HTG2190
Rev. 1.00
21
June 29, 2001
tion(s) in the program memory. Only the pro-
gram counter are pushed and A15~A13 bits
onto the stack. If the contents of the register
and Status register (STATUS) are altered by
the interrupt service program which corrupt
the desired control sequence, the contents must
be saved first.
External interrupt is triggered by a high to low
transition of INT which sets the related inter-
rupt request flag (EIF; bit 4 of INTC0). When
the interrupt is enabled, and the stack is not
full and the external interrupt is active, a sub-
routine call to location 04H will occur. The in-
terrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
The internal Timer/Event Counter 0 interrupt
is initialized by setting the Timer/Event Coun-
ter 0 interrupt request flag (T0F; bit 5 of
INTC0), caused by a Timer/Event Counter 0
overflow. When the interrupt is enabled, and
the stack is not full and the T0F bit is set, a sub-
routine call to location 08H will occur. The re-
lated interrupt request flag (T0F) will be reset
and the bit cleared to disable further inter-
rupts.
TheTimer/EventCounter1andtimer2/3inter-
rupt is operated in the same manner as
Timer/Event Counter 0. The related interrupt
control bits ET1I and T1F of Timer/Event
Counter 1 are bit 3 and bit 6 of INTC0 respec-
tively. While ET2I/ET3I and T2F/T3F are the
related control bits and the related request
flags of TMR2/TMR3, which locate at bit0/bit1
and bit4/bit5 of the INTC1 respectively.
During the execution of an interrupt subroutine,
other interrupt acknowledgments are held until
the RETI instruction is executed or the EMI bit
andtherelatedinterruptcontrolbitaresetto1(of
course, if the stack is not full). To return from the
interruptsubroutine,theRETorRETIinstruction
may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are en-
abled. In the case of simultaneous requests, the
following table shows the priority that is
applied. These can be masked by resetting the
EMI bit.
Register
Bit No.
Label
Function
INTC0
0
EMI
Master (Global) interrupt
(1=enable; 0=disable)
1
EEI
External interrupt
(1=enable; 0=disable)
2
ET0I
Timer/Event Counter 0 interrupt
(1=enable; 0=disable)
3
ET1I
Timer/Event Counter 1 interrupt
(1=enable; 0=disable)
4
EIF
External interrupt request flag
(1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag.
(1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag.
(1=active; 0=inactive)
7
Unused bit, read as "0"
INTC0 register
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