HTG2190
Rev. 1.00
12
June 29, 2001
Instruction
Table Location
*15 *14 *13 *12 *11 *10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
#7
#6
#5
#4
#3
#2
#1
#0
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: @7~@0: TBLP register bit7~bit0
*15~*0: Program ROM table address bit15~bit0
#7~#0: TBHP register bit7~bit0
Location 010H/014H
This area is reserved for the timer 2/3 inter-
rupt service program. If a timer interrupt re-
sulting from a timer 2/3 overflow, and if the
interrupt is enabled and the stack is not full,
the program will jump to location 010H/014H
and begins execution.
Location 018H
This area is reserved for the PWM D/A buffer
empty interrupt service program. After the
system latch a D/A code at RAM address 28H,
the interrupt is enable, and the stack is not
full, the program begins execution at location
018H.
Location 020H
For best condition, this location is reserved as
the beginning when writing a program.
ROM Bank 1~7 (BP5~BP7=001B~111)
The range of the ROM starts from n000H to
(n+1)FFFH. (n=2,4,6,8,10,12,14)
Table location
Any location in the ROM space can be used as
look up table. The instructions TABRDC [m]
(use for any bank) and TABRDL [m] (only
used for last page of program ROM) transfers
the contents of the lower-order byte to the
specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of
the lower-order byte in the table is
well-defined, the higher-order byte of the ta-
ble word are transferred to the TBLH. The
Table Higher-order byte register (TBLH) is
read only. The Table Pointer (TBHP, TBLP)
isaread/writeregister(1FH,07H),usedtoin-
dicate the table location. Before accessing the
table, the location must be placed in TBLP.
The TBLH is read only and cannot be re-
stored. If the main routine and the ISR (Inter-
rupt Service Routine) both employ the table
read instruction, the contents of the TBLH in
the main routine are likely to be changed by
the table read instruction used in the ISR. If
this happens errors can occur. In other words,
using the table read instruction in the main
routine and the ISR simultaneously should be
avoided. However, if the table read instruc-
tionhastobeappliedinboththemainroutine
and the ISR, the interrupt(s) should be dis-
abled prior to the table read instruction. It
should not be enabled until the TBLH has
been backed up. All table related instructions
need two cycles to complete the operation.
These areas may function as normal program
memory depending upon requirements.
Stack register
STACK
This is a special part of memory which is used
to save the contents of the program counter
(PC) only. The stack is organized into 8 levels
and is neither part of the data nor program
space, and is neither readable nor writeable.
The activated level is indexed by the stack
pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt ac-
knowledgment, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be re-
corded but the acknowledge will be inhibited.
When the stack pointer is decremented (by RET
or RETI), the interrupt will be serviced. This fea-
ture prevents stack overflow allowing the pro-
grammer to use the structure more easily.