參數(shù)資料
型號: HT9480
廠商: Holtek Semiconductor Inc.
英文描述: Pager Controller
中文描述: 傳呼機控制器
文件頁數(shù): 7/57頁
文件大?。?/td> 1541K
代理商: HT9480
E xecution flow
System Architecture
Execution flow
The HT9480 system clock can be derived from
either a crystal or an RC oscillator. It is inter-
nally divided into four non-overlapping clocks
denoted by P1, P2, P3, and P4. E ach instruction
cycle consists of T1 to T4.
Instruction fetching and execution are pipe-
lined in such a way that a fetch takes an in-
struction cycle while decoding and execution
take the next instruction cycle. The pipelining
scheme causes each instruction to effectively
execute within a cycle. If an instruction changes
the content of the program counter two cycles
are required to complete the instruction.
Program counter – PC
The program counter (PC) is 13-bit wide and
controls the program ROM instruction se-
quence execution. The contents of the PC can
specify a of maximum 8192 addresses.
Mode
Program Counter
*8
*7
0
0
*12
0
*11
0
*10
0
*9
0
*6
0
*5
0
*4
0
*3
0
*2
0
*1
0
*0
0
Initial reset
Data ready interrupt and
battery fail interrupt
Programmable timer
interrupt
Timer/event Counter
interrupt
Skip
Loading PCL
J ump, call branch
Return from subroutine
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
PC+2
@6
#6
S6
*12
#12
S12
*11
#11
S11 S10
*10
#10
*9
#9
S9
*8
#8
S8
@7
#7
S7
@5
#5
S5
@4
#4
S4
@3
#3
S3
@2
#2
S2
@1
#1
S1
@0
#0
S0
Program counter
Notes:
*12~*0: Program counter bits
#12~#0: Instruction code bits
S12~S0: Stack register bits
@7~@0: PCL bits
HT9480
7
23th Feb ’98
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