參數(shù)資料
型號： HT9480
廠商： Holtek Semiconductor Inc.
英文描述： Pager Controller
中文描述： 傳呼機控制器
文件頁數(shù)： 18/57頁
文件大?。?/td> 1541K
代理商： HT9480
L abels (T MR C0
and T MR C1)
Bits
F unction
—
0~2
Unused bits, read as “0”
TE
3
To define the TMR0 and TMR1 active edge of programmable timer
counter and timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer counting
(0=disabled; 1=enabled)
5
Unused bits, read as “0”
TM0
TM1
6
7
To define the operation mode
01=E vent count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC register
Programmable timer counter and
timer/event counter
The programmable timer counter (TMR0) and
timer/event counter (TMR1) are constructed us-
ing the same structure. Both counters contain
an 8–bit programmable count-up counter,
whose clocks may come from an external
source or from the system clock divided by 4.
If the internal instruction clock is selected, only
one reference time-base is provided. The exter-
nal clock input allows the user to count external
events, measure time intervals or pulse widths,
or generate an accurate time base. The clock of
the programmable timer counter should come
from the external clock of the 75Hz for Real
Time Clock (RTC) if a 76.8kHz crystal is used.
There are two sets of registers related to the
programmable timer counter and to the
timer/event counter namely, TMR0 (0DH) and
TMRC0 (0E H) and TMR1 (10H) and TMRC1
(11H). There are also two physical registers
mapped to the TMR0 and TMR1 locations:
Writing to TMR0 and TMR1 puts the starting
value in the programmable timer counter and
in the timer/event counter preload registers,
while reading them gets the contents of the two
counters. TMRC0 and TMRC1 are control reg-
isters used to define some timer options.
The TM0 and TM1 bits define the operation
mode. The event count mode is used to count
external events, which means that the clock
source may come from either a 256Hz generator
(for TMR0) or an external pin (for TMR1). The
timer mode functions as a normal timer, with
the clock source coming from the instruction
clock or from the outputs of the TMR1 prescaler
(TMR0 cannot be used in this mode). The pulse
width measurement mode can be used to count
the high or low level duration of the external
signal TMR1, TMR0 is also disabled in this
mode. The counting is based on the system
clock.
In the event count or timer mode, once the
programmable timer counter or timer/event
counter starts counting, it will count from the
current contents in the counter to FFH. Once an
overflow occurs, the counter is reloaded from its
counter preload register and generates an in-
terrupt request flag (T0F; bit 5 of INTC and
T1F; bit 6 of INTC for programmable timer
counter and timer/event counter, respectively).
On the other hand, in the pulse width measure-
ment mode with the TON bit equal to one, when
the TMR1 receives a transient from low to high
(or high to low depending upon the TE bit) it
will start counting until the TMR1 returns to
the original level and resets the TON as well.
HT9480
18
23th Feb ’98
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