參數(shù)資料
型號： HT9480
廠商： Holtek Semiconductor Inc.
英文描述： Pager Controller
中文描述： 傳呼機控制器
文件頁數(shù)： 13/57頁
文件大?。?/td> 1541K
代理商： HT9480
ready interrupt bit (DR; bit 7 of 1E H). Once the
data ready interrupt is triggered, the stack is
not full, and the EMI bit is set, a subroutine call
to location 04H will occur. The related interrupt
request flag (E IF) will, however, be reset, and
the E MI bit cleared to disable further inter-
rupts. This interrupt should be processed care-
fully if the battery fail interrupt is activated as
well.
The battery fail interrupt, on the other hand, is
triggered by a high to low transition on BAF.
When the battery fail interrupt is enabled, the
stack is not full, and the interrupt request flag
(E IF; bit 4 of INTC) is set, a subroutine call to
location 04H will occur. The related interrupt
request flag (E IF) will also be reset, and the
E MI bit be cleared to disable other interrupts.
The programmable timer interrupt is automat-
ically triggered at a rate of 256Hz/N (where the
value of N ranges from 1 to 256), and then the
interrupt request flag (T0F; bit 5 of INTC) is
set. When the timer interrupt is enabled, the
stack is not full, and the programmable timer
interrupt is activated, a subroutine call to loca-
tion 08H will occur. Then, the related interrupt
request flag (T0F) will be reset, and the E MI bit
cleared to disable other interrupts.
The timer/event counter interrupt is initialized
by setting the timer/event counter interrupt re-
quest flag (T1F; bit 6 of INTC), which is nor-
mally caused by a timer overflow. When the
interrupt is enabled, the stack is not full, and
the T1F bit is set, a subroutine call to location
0CH will occur. The related interrupt request
flag (T1F) will be reset, and the EMI bit cleared
to disable further interrupts.
During the execution of an interrupt subrou-
tine, other interrupt acknowledgments are all
held until the “RE TI” instruction is executed, or
the E MI bit and the related interrupt control bit
are both set to 1 (if the stack is not full). To
return from the interrupt subroutine, a “RE T”
or “RE TI” instruction may be invoked. RE TI
will set the E MI bit to enable an interrupt service,
but RET will not.
The interrupts are serviced between the rising
edges of the two adjacent T2 clocks. In case of
simultaneous requests, the following table
shows the priority that is applied. These can be
masked by resetting the E MI bit.
R egister
Bit No.
L abel
F unction
INTC
(0BH)
0
E MI
Controls the master (global) interrupt
(1=enabled; 0=disabled)
1
E E I
Controls the data ready and battery fail interrupts
(1=enabled; 0=disabled)
2
E T0I
Controls the programmable timer interrupt
(1=enabled; 0=disabled)
3
E T1I
Controls the timer/event counter interrupt
(1=enabled, 0=disabled)
4
E IF
Internal data ready and battery fail interrupt request flag
(1=active; 0=inactive)
5
T0F
Internal programmable timer interrupt request flag
(1=active; 0=inactive)
6
T1F
Timer/event counter request flag
(1=active; 0=inactive)
7
--
Unused bit, read as “0”
INTC register
HT9480
13
23th Feb ’98
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