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參數(shù)資料
| 型號： | HT47C20L |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 33/55頁 |
| 文件大?。?/td> | 341K |
| 代理商： | HT47C20L |
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HT47C20L
33
January 18, 2000
Register Bit No.
Label
Read/Write Reset
Function
RTCC
(09H)
0
1
2
RT0
RT1
RT2
R/W
1
1
1
8 to 1 multiplexer control inputs to select the
real time clock prescaler output
3
BON
R/W
0
Voltage low detector enable/disable control bit
0 indicates voltage detector is disabled
1 indicates voltage detector is enabled
4
Undefined bit, read as unknown
5
BLF
R
X
Battery low flag
0 indicates that the voltage is not low
1 indicates that the voltage is low
6, 7
Unused bits, read as 0
RTCC Register
Note: X means invalid
Voltage low detector
The HT47C20L provides a voltage low detector
for battery system application. If the battery
voltage is lower than the specified value, the
battery low flag (BLF; bit 5 of RTCC) is set. The
specified value is 1.2V 0.1V. The voltage low
detector circuit can be turn On or Off by writing
a 1 or a 0 to BON (bit 3 of RTCC register). A
delay time of 1ms is required to monitor the
BLF after setting the BON bit. The BLF is in-
valid when the BON is cleared as 0 . The volt-
age low detector can be disabled by mask
option.
Buzzer
HT47C20L provides a pair of buzzer output BZ
and BZ, which share pins with PA0 and PA1 re-
spectively, determined by mask option. Its out-
put frequency can also be selected by mask
option.
When the buzzer function is selected, setting
PA.0 and PA.1 0 simultaneously will enable
the buzzer output and setting PA.0 1 will dis-
able the buzzer output and setting PA.0 0 and
PA.1 1 will only enable the BZ output and dis-
able the BZ output.
PA1
PA0
Function
0
(CLR PA.1)
0
(CLR PA.0)
PA0= BZ
PA1= BZ
1
(SET PA.1)
0
(CLR PA.0)
PA0= BZ
PA1= 0
X
1
(SET PA.0)
PA0= 0
PA1= 0
Buzzer enable
Programmable frequency divider
PFD
The PFD output shares pin with PA3 as deter-
mined by mask option.
When the PFD option is selected, setting PA3
0 will enable the PFD output and setting PA3
1 will disable the PFD output and PA3 output
at low level.
PA3
Function
0 (CLR PA.3)
PA3= PFD Output
1 (SET PA.3)
PA3= 0
PFD output frequency=
1
2
timer overflow period
1
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