HT47C20L
28
January 18, 2000
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PA0/BZ, PA1/BZ input/output lines
Input/output ports
There are 8-bit bidirectional input/output port
and 4-bit input port in the HT47C20L, labeled
PAand PB which are mapped to the data mem-
ory of [12H] and [14H] respectively. The high
nibbleofthePAisNMOSoutputandinputwith
pull-high resistors. The low nibble of the PAcan
be used for input/output or output operation by
selecting NMOS or CMOS output by mask op-
tion. Each bit on the PA can be configured as a
wake-upinputandthelownibbleofthePAwith
or without pull-high resistors by mask option.
PB can only be used for input operation, and
each bit on the port can be configured with pull
high resistor. Both are for the input operation,
these ports are non-latched, that is, the inputs
should be ready at the T2 rising edge of the in-
struction MOV A, [m] (m=12H or 14H). For
PA output operation, all data are latched and
remain unchanged until the output latch is re-
written.
When the structures of PAare open drain NMOS
type, it should be noted that, before reading data
from the pads a 1 should be written to the re-
lated bits to disable the NMOS device. That is
done first before executing the instruction MOV
A, 0FFH and MOV [12H], A to disable the re-
lated NMOS device, and then MOV A, [12H] to
get a stable data.
After chip reset, these input lines remain at a
high level or are left floating (by mask option).
Some instructions first input data and then fol-
low the output operations. For example, SET
[m].i , CLR [m].i , CPL [m] , CPLA [m] read
the entire port states into the CPU, execute the
definedoperations(bit-operation),andthenwrite
theresultsbacktothelatchesortotheaccumula-
tor. Each bit of the PAoutput latches can not use
these instruction, which may change the input
lines to output lines (when the input lines are at
low level).