參數(shù)資料
型號(hào): HT47C20L
廠商: Holtek Semiconductor Inc.
元件分類(lèi): 數(shù)學(xué)處理器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁(yè)數(shù): 26/55頁(yè)
文件大小: 341K
代理商: HT47C20L
HT47C20L
26
January 18, 2000
The bit4~bit7 of ADCR decides which resistor
andcapacitorcomposeanoscillationcircuitand
input to TMRBH and TMRBL.
The TN0, TN1 and TN2 bits of TMRC define
the clock source of timer A. It is suggested that
the clock source of timer Ause the system clock,
instruction clock or real time clock prescaler
clock.
The TON bit (bit 4 of TMRC) is set 1 , the
timer A and timer B will start counting until
timer A or timer B overflows, the timer/event
counter generates the interrupt request flag
(TF ; bit 4 of INTC1) and the timer A and timer
B stop counting and reset the TON bit to 0 at
the same time.
If the TON bit is 1 , the TMRAH, TMRAL,
TMRBH and TMRBL cannot be read or written
to. Only when the timer/event counter is off and
when the instruction MOV is used could those
four registers be read or written to.
Example for RC type AD converter mode (Timer A overflow):
clr tmrc
clr adcr.1
; set timer mode
clr intc1.4
; clear timer/event counter interrupt request flag
mov a, low (65536-1000)
; give timer A initial value
mov tmrbl, a
; count 1000 time and then overflow
mov a, high (65536-1000)
mov tmrbh, a
mov a, 00010010b
; RS0~CS0; set RC type ADC mode; set Timer A overflow
mov adcr,a
mov a, 00h
; give timer B initial value
mov tmrbl, a
mov a, 00h
mov tmrbh, a
mov a, 00110000b
; timer A clock source=T1 and timer on
mov tmrc, a
p10:
clr wdt
snz intcl.4
; polling timer/event counter interrupt request flag
jmp p10
clr intcl.4
; clear timer/event counter interrupt request flag
; program continue
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