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參數(shù)資料
| 型號： | HT47C20L |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 11/55頁 |
| 文件大?。?/td> | 341K |
| 代理商： | HT47C20L |
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HT47C20L
11
January 18, 2000
Instruction(s)
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *10~*0: Bits of table location
@7~@0: Bits of table pointer
P10 P8: Bits of current program counter
tion. Before accessing the table, the location
must be placed in TBLP. The TBLH is read
only and cannot be restored. If the main rou-
tine and the ISR (interrupt service routine)
both employ the table read instruction, the
contents of the TBLH in the main routine are
likely to be changed by the table read instruc-
tion used in the ISR. Errors can occur. In
other words using the table read instruction
in the main routine and the ISR simulta-
neously should be avoided. However, if the ta-
ble read instruction has to be applied in both
the main routine and the ISR, the interrupt is
supposed to be disabled prior to the table read
instruction. It will not be enabled until the
TBLH has been backed up. All table related
instructions need two cycles to complete the
operation. These areas may function as nor-
mal program memory depending upon the re-
quirements.
Stack register
STACK
This is a special part of the memory which is
used to save the contents of the program counter
(PC)only.Thestackisorganizedintofourlevels
and is neither part of the data nor part of the
program space, and is neither readable nor
writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt ac-
knowledgment, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be
recorded but the acknowledgment will be inhib-
ited. When the stack pointer is decremented (by
RET or RETI), the interrupt will be serviced.
This feature prevents stack overflow allowing
the programmer to use the structure more eas-
ily. In a similar case, if the stack is full and a
CALL is subsequently executed, stack over-
flow occurs and the first entry will be lost (only
the most recent four return addresses are
stored).
Data memory
RAM
The data memory is designed with 83 8 bits.
The data memory is divided into two functional
groups: special function registers and general
purposedatamemory(64 8).Mostareread/write,
but some are read only.
Thespecialfunctionregistersincludetheindirect
addressing register 0 (00H), the memory pointer
register 0 (MP0; 01H), the indirect addressing
register 1 (02H), the memory pointer register 1
(MP1;03H), the bank pointer (BP;04H), the accu-
mulator (ACC;05H), the program counter
lower-order byte register (PCL;06H), the table
pointer (TBLP;07H), the table higher-order byte
register (TBLH;08H), the real time clock control
register (RTCC;09H), the status register
(STATUS;0AH), the interrupt control register 0
(INTC0;0BH), the I/O registers (PA;12H,
PB;14H), the interrupt control register 1
(INTC1;1EH), the timer/event counter A
higher order byte register (TMRAH; 20H), the
timer/event counter A lower order byte register
(TMRAL; 21H), the timer/event counter control
register (TMRC; 22H), the timer/event counter B
higher order byte register (TMRBH; 23H), the
timer/event counter B lower-order byte register
(TMRBL; 24H), and the RC oscillator type A/D
converter control register (ADCR; 25H). The re-
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