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參數(shù)資料
| 型號： | HT47C20L |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 22/55頁 |
| 文件大?。?/td> | 341K |
| 代理商： | HT47C20L |
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HT47C20L
22
January 18, 2000
tents in the timer/event counter (TMRAH and
TMRAL) to FFFFH. Once overflow occurs, the
counter is reloaded from the timer/event coun-
ter preload register (TMRBH and TMRBL) and
generates the corresponding interrupt request
flag (TF; bit 4 of INTC1) at the same time.
In the pulse width measurement mode with
the TON and TE bits equal to one, once the
TMR has received a transient from low to high
(or high to low if the TE bit is 0) it will start
counting until the TMR returns to the original
level and resets the TON. The measured result
will remain in the timer/event counter even if
the activated transient occurs again. In other
words, only one cycle measurement can be done.
Until setting the TON, the cycle measurement
will function again as long as it receives fur-
ther transient pulse. Note that in this operation
mode, the timer/event counter starts counting
not according to the logic level but according to
the transient edges. In the case of counter over-
flow, the counter is reloaded from the
timer/event counter preload register and is-
sues interrupt request just like the other three
modes.
To enable the counting operation, the timer On
bit (TON; bit 4 of TMRC) should be set to 1. In
the pulse width measurement mode, the TON
will automatically be cleared after the mea-
surement cycle is completed. But in the other
three modes, the TON can only be reset by in-
structions. The overflow of the timer/event
counter is one of the wake-up sources and can
also be applied as a PFD (programmable fre-
quency divider) output at PA3 by mask option.
No matter what the operation mode is, writing
a 0 to ETI can disable the corresponding inter-
rupt service. When the PFD function is se-
lected, executing
CLR PA.3
enable the PFD output and executing
PA.3
instruction to disable the PFD output
and PA.3 output low level.
instruction to
SET
In the case of timer/event counter Off condition,
writing data to the timer/event counter preload
register also reloads that data to the timer/ event
counter. But if the timer/event counter turns
On, data written to the timer/event counter
preload register is kept only in the timer/event
counter preload register. The timer/event coun-
ter will still operate until overflow occurs.
When the timer/event counter (reading
TMRAH) is read, the clock will be blocked to
avoid errors. As this may results in a counting
error, this must be taken into consideration by
the programmer.
Label
(TMRC)
Bits
Function
0~2 Unused bits, read as 0
TE
3
To define the TMR active edge of timer/event counter
(0= active on low to high; 1= active on high to low)
TON
4
To enable/disable timer counting
(0= disabled; 1= enabled)
TN0
TN1
TN2
5
6
7
To define the operating mode (TN2, TN1, TN0)
000= Timer mode (system clock)
001= Timer mode (system clock/4)
010= Timer mode (real time clock output)
011= A/D clock mode (RC oscillation decided by ADCR register)
100= Event counter mode (external clock)
101= Pulse width measurement mode (system clock/4)
110= Unused
111= Unused
TMRC register
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