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參數(shù)資料
| 型號： | HT47C20L |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 15/55頁 |
| 文件大?。?/td> | 341K |
| 代理商： | HT47C20L |
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HT47C20L
15
January 18, 2000
External interrupt is triggered by a high to low
transition of INT and the related interrupt
request flag (EIF; bit 4 of INTC0) will be set.
When the interrupt is enabled, and the stack is
not full and the external interrupt is active, a sub-
routine call to location 04H will occur. The inter-
rupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
The internal timer/event counter interrupt is
initialized by setting the timer/event counter
interrupt request flag (TF; bit 4 of INTC1),
caused by a timer A or timer B overflow. When
the interrupt is enabled, and the stack is not
full and the TF bit is set, a subroutine call to lo-
cation 10H will occur. The related interrupt re-
quest flag (TF) will be reset and the EMI bit
cleared to disable further interrupts.
The time base interrupt is initialized by setting
the time base interrupt request flag (TBF; bit 5
of INTC0), caused by a regular time base sig-
nal. When the interrupt is enabled, and the
stack is not full and the TBF bit is set, a subrou-
tine call to location 08H will occur. The related
interrupt request flag (TBF) will be reset and
the EMI bit cleared to disable further inter-
rupts.
The real time clock interrupt is initialized by
setting the real time clock interrupt request
flag (RTF; bit 6 of INTC0), caused by a regular
real time clock signal. When the interrupt is en-
abled, and the stack is not full and the RTF bit
is set, a subroutine call to location 0CH will oc-
cur. The related interrupt request flag (RTF)
will be reset and the EMI bit cleared to disable
further interrupts.
Duringtheexecutionofaninterruptsubroutine,
other interrupt acknowledgments are held until
the RETI instruction is executed or the EMI bit
and the related interrupt control bit are set to 1
(if the stack is not full). To return from the inter-
rupt subroutine, RET or RETI instruction may
be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET does not.
Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are en-
abled. In the case of simultaneous requests the
following table shows the priority that is ap-
plied. These can be masked by resetting the
EMI bit.
No.
Interrupt Source Priority Vector
a
External interrupt
1
04H
b
Time base interrupt
2
08H
c
Real time clock
interrupt
3
0CH
d
Timer/event counter
interrupt
4
10H
The external interrupt request flag (EIF), real
time clock interrupt request flag (RTF), time
base interrupt request flag (TBF), enable exter-
nalinterruptbit(EEI),enablerealtimeclockin-
terrupt bit (ERTI), enable time base interrupt
bit (ETBI), and enable master interrupt bit
(EMI) constitute an interrupt control register 0
(INTC0) which is located at 0BH in the data
memory. The timer/event counter interrupt re-
quest flag (TF), enable timer/event counter in-
terrupt bit (ETI) on the other hand, constitute
an interrupt control register 1 (INTC1) which is
located at 1EH in the data memory. EMI, EEI,
ETI, ETBI, and ERTI are used to control the
enabling/disabling of interrupts. These bits
prevent the requested interrupt being serviced.
Once the interrupt request flags (RTF, TBF, TF,
EIF) are set, they remain in the INTC1 or
INTC0respectivelyuntiltheinterruptsareser-
viced or cleared by a software instruction.
It is recommended that a program does not use
the
CALL subroutine
subroutine. Interrupts often occur in an unpre-
dictable manner or need to be serviced immedi-
ately in some applications. If only one stack is
left, and enabling the interrupt is not well con-
trolled, the original control sequence will be
damaged once the CALL subroutine operates
in the interrupt subroutine.
within the interrupt
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