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參數(shù)資料
| 型號： | HT47C20 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 352K |
| 代理商： | HT47C20 |
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HT47C20
19
January 18, 2000
Once a wake-up event occurs, it takes 1024 t
SYS
(system clock period) to resume normal opera-
tion. In other words, a dummy period will be in-
serted after the wake-up. If the wake-up results
from an interrupt acknowledgment, the actual
interrupt subroutine execution is delayed by
one more cycle. If the wake-up results in the
next instruction execution, this will execute im-
mediately after a dummy period has finished.
To minimize power consumption, all the I/O
pins should be carefully managed before enter-
ing the HALT status.
Reset
Therearethreewaysinwhicharesetmayoccur.
RES reset during normal operation
RES reset during HALT
WDTtime-outresetduringnormaloperation
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a warm reset that just resets the PC
and SP leaving the other circuits in their origi-
nal state. Some registers remain unchanged
during any other reset conditions. Most regis-
ters are reset to the initial condition when the
reset conditions are met. By examining the PD
and TO flags, the program can distinguish be-
tween different chip resets .
TO
PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal
operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
Note: u means unchanged .
To guarantee that the system oscillator has
started and stabilized, the SST (System
Start-up Timer) provides an extra delay. There
is an extra delay of 1024 system clock pulses
when the system awakes from the HALT state
or when the system powers up.
The functional unit chip reset status are shown
below.
PC
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC, Time
Base
Clear. After master
reset, begin counting
Timer/eventcounter Off
Input/output ports
Input mode
SP
Points to the top of
the stack
!
(
& " (
Reset timing chart
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