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參數(shù)資料
| 型號： | HT47C20 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 13/56頁 |
| 文件大?。?/td> | 352K |
| 代理商： | HT47C20 |
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HT47C20
13
January 18, 2000
Arithmetic and logic unit
ALU
This circuit performs 8-bit arithmetic and logic
operation. The ALU provides the following
functions:
Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data op-
eration but can change the status register.
Status register
STATUS
This8-bitregister(0AH)containsthezeroflag(Z),
carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD) and
watchdog time-out flag (TO). It also records the
status information and controls the operation se-
quence.
With the exception of the TO and PD flags, bits
in the status register can be altered by instruc-
tions like most other registers. Any data writ-
ten into the status register will not change the
TO or PD flags. In addition it should be noted
that operations related to the status register
may give different results from those intended.
The TO and PD flags can only be changed by
the watchdog timer overflow, system power-up,
clearing the watchdog timer and executing the
HALT instruction.
The Z, OV, AC and C flags generally reflect the
status of the latest operations.
In addition, on entering the interrupt sequence
or executing the subroutine call, the status reg-
ister will not be pushed onto the stack automat-
ically. If the contents of the status are
important and if the subroutine can corrupt the
status register, precautions must be taken to
save it properly.
Interrupts
The HT47C20 provides an external interrupt,
an internal timer/event counter interrupt, an
internal time base interrupt, and an internal
real time clock interrupt. The interrupt control
register 0 (INTC0;0BH) and interrupt control
register 1 (INTC1;1EH) both contain the inter-
rupt control bits to set the enable/disable and
interrupt request flags.
Labels
Bits
Function
C
0
Cissetiftheoperationresultsinacarryduringanadditionoperationorifabor-
row does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
ACissetiftheoperationresultsinacarryoutofthelownibblesinadditionorno
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared when either a system power-up or executing the CLR WDT in-
struction. PD is set by executing the HALT instruction.
TO
5
TO is cleared by a system power-up or executing the CLR WDT or HALT in-
struction. TO is set by a WDT time-out.
6
Undefined, read as 0
7
Undefined, read as 0
STATUS register
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