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參數(shù)資料
| 型號： | HT46C24 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | A/D Type 8-Bit MCU |
| 中文描述： | 的A / D型8位微控制器 |
| 文件頁數(shù)： | 9/49頁 |
| 文件大?。?/td> | 393K |
| 代理商： | HT46C24 |
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HT46R24/HT46C24
Rev. 1.50
9
May 3, 2004
in operations to either bank 1 or bank 2. Directly ad-
dressing the Data Memory will always result in Bank 0
being accessed irrespective of the value of BP.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1(03H) respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation. The
function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining corresponding indirect
addressing registers.
Accumulator
ACC
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the RAM and capable
of operating with immediate data. The data movement
between two data memory locations must pass through
the accumulator.
Arithmetic and Logic Unit
ALU
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register
STATUS
The status register (0AH) is 8 bits wide and contains, a
carryflag(C),anauxiliarycarryflag(AC),azeroflag(Z),
an overflow flag (OV), a power down flag (PDF), and a
Watchdog time-out flag (TO). It also records the status
information and controls the operation sequence. Ex-
cept for the TO and PDF flags, bits in the status register
can be altered by instructions similar to other registers.
DatawrittenintothestatusregisterdoesnotaltertheTO
or PDF flags. Operations related to the status register,
however, may yield different results from those in-
tended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the HALT instruc-
tion.
The Z, OV, AC, and C flags reflect the status of the latest
operations. On entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status is important, and if the subroutine is likely to
corrupt the status register, the programmer should take
precautions and save it properly.
Interrupts
The device provides an external interrupt, two internal
timer/eventcounterinterrupt,theA/Dconverterinterrupt
and the I
2
C Bus interrupts. The interrupt control register
0 (INTC0;0BH) and interrupt control register 1
(INTC1;1EH) contains the interrupt control bits to set the
enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
Labels
Bits
Function
C
0
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC
1
ACissetifanoperationresultsinacarryoutofthelownibblesinadditionornoborrowfromthe
high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV
3
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF
4
PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by ex-
ecuting the HALT instruction.
TO
5
TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is
set by a WDT time-out.
6, 7
Unused bit, read as 0
Status Register
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| HT46R24 | A/D Type 8-Bit MCU |
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相關(guān)代理商/技術(shù)參數(shù) |
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