參數(shù)資料
型號(hào): HT46C24
廠商: Holtek Semiconductor Inc.
英文描述: A/D Type 8-Bit MCU
中文描述: 的A / D型8位微控制器
文件頁數(shù): 8/49頁
文件大?。?/td> 393K
代理商: HT46C24
HT46R24/HT46C24
Rev. 1.50
8
May 3, 2004
value from the stack. After a chip reset, the SP will point
to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointerisdecremented(byRETorRETI),theinterruptis
serviced. This feature prevents stack overflow, allowing
the programmer to use the structure more easily. If the
stack is full and a CALL is subsequently executed,
stack overflow occurs and the first entry will be lost (only
the most recent 16 return addresses are stored).
Data Memory
RAM
The data memory (RAM) is designed with 424 8 bits,
and is divided into two functional groups, namely; spe-
cial function registers (40 8 bits) and general purpose
data memory (Bank 0:192 8 bits and Bank 1:192 8
bits) most of which are readable/writeable, although
some are read only.
The special function registers are overlapped in any
banks. Of the two types of functional groups, the special
function registers consist of an Indirect addressing reg-
ister 0 (00H), a Memory pointer register 0 (MP0;01H),
an Indirect addressing register 1 (02H), a Memory
pointer register 1 (MP1;03H), a Bank pointer (BP;04H),
an Accumulator (ACC;05H), a Program counter
lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), a Timer/Event
Counter 0 (TMR0H:0CH; TMR0L:0DH), a Timer/Event
Counter 0 control register (TMR0C;0EH), a Timer/Event
Counter 1 (TMR1H:0FH; TMR1L:10H), a Timer/Event
Counter 1 control register (TMR1C; 11H), Interrupt con-
trol register 1 (INTC1;1EH), PWM data register
(PWM0;1AH, PWM1;1BH, PWM2;1CH, PWM3;1DH),
the I
2
C Bus slave address register (HADR;20H), the I
2
C
Bus control register (HCR;21H), the I
2
C Bus status reg-
ister (HSR;22H), the I
2
C Bus data register
(HDR;23H),the A/D result lower-order byte register
(ADRL;24H), the A/D result higher-order byte register
(ADRH;25H), the A/D control register (ADCR;26H), the
A/D clock setting register (ACSR;27H), I/O registers
(PA;12H, PB;14H, PC;16H, PD;18H, PF; 28H) and I/O
control registers (PAC;13H, PBC;15H, PCC;17H,
PDC;19H, PFC;29H). The remaining space before the
40H is reserved for future expanded usage and reading
these locations will get 00H . The space before 40H is
overlapping in each bank. The general purpose data
memory, addressed from 40H to FFH (Bank0; BP=0 or
Bank1; BP=1), is used for data and control information
under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
CLR [m].i . They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H). The
space before 40H is overlapping in each bank.
After first setting up BP to the value of 01H or 02H to
accesseitherbank1orbank2respectively,thesebanks
must then be accessed indirectly using the Memory
Pointer MP1. With BP set to a value of either 01H or
02H , using MP1 to indirectly read or write to the data
memory areas with addresses from 40H~FFH will result
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RAM Mapping
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