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參數(shù)資料
| 型號(hào)： | HB52RF1289E2 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 1 GB Registered SDRAM DIMM(1GB 寄存同步DRAM DIMM) |
| 中文描述： | 1 GB的注冊(cè)SDRAM的內(nèi)存（1GB的寄存同步的DRAM內(nèi)存） |
| 文件頁(yè)數(shù)： | 17/21頁(yè) |
| 文件大小： | 95K |
| 代理商： | HB52RF1289E2 |
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HB52RF1289E2-75B
17
Relationship Between Frequency and Minimum Latency
Pin Functions
CK0 to CK3 (input pin):
CK is the master clock input to this pin. The other input signals are referred at
CK rising edge.
S0 to S3 (input pin):
When S is Low, the command input cycle becomes valid. When S is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins):
Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the com-
bination of their voltage levels. For details, refer to the command operation section.
Parameter
Frequency (MHz)
HB52RF1289E2-75B
133
t
CK
(ns)
Active command to column command (same bank) I
RCD
Active command to active command (same bank)
HITA-
CHI
Symbol
PC100
Sym-
bol
7.5
3
9
Notes
1
= [I
RAS
+
I
RP
]
1
1
I
RC
Active command to precharge command (same
bank)
Precharge command to active command (same
bank)
Write recovery or data-in to precharge command
(same bank)
Active command to active command (different bank) I
RRD
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input
I
RAS
6
I
RP
3
1
I
DPL
Tdpl
2
1
2
2
5
1
2
= [I
DPL
+
I
RP
]
= [I
RC
]
3
I
SREX
I
APW
Tsrx
Tdal
I
SEC
9
Precharge command to high impedance
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
Column command to column command
Write command to data in latency
DQMB to data in
DQMB to data out
CKE to CK disable
Register set to active command
S to command disable
Power down exit to command input
I
HZP
I
APR
Troh
4
0
I
EP
I
CCD
I
WCD
I
DID
I
DOD
I
CLE
I
RSA
I
CDD
I
PEC
–3
1
1
1
3
2
3
0
1
Tccd
Tdwd
Tdqm
Tdqz
Tcke
Tmrd
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HB52RF329E2 | 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM) |
| HB52RF648DC-B | 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword 】 64-bit, 133/100 MHz Memory Bus, 2-Bank Module (16 pcs of 32 M 】 8 components) PC133/100 SDRAM |
| HB52RD648DC-B | 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword 】 64-bit, 133/100 MHz Memory Bus, 2-Bank Module (16 pcs of 32 M 】 8 components) PC133/100 SDRAM |
| HB52RF649DC | 512MB Unbuffered SDRAM S.O.DIMM |
| HB52RD649DC-A6B | 512MB Unbuffered SDRAM S.O.DIMM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HB52RF1289E2-75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:x72 SDRAM Module |
| HB52RF1289E2U-75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC133 SDRAM |
| HB52RF328GB-75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM Micro DIMM |
| HB52RF328GB-75BL | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM Micro DIMM |
| HB52RF328GB-B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Unbuffered SDRAM Micro DIMM |
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