參數(shù)資料
型號(hào)： GS4900BCNE3
廠商： Gennum Corporation
英文描述： SD Clock and Timing Generator with GENLOCK
中文描述： 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁數(shù)： 75/95頁
文件大?。?/td> 898K
代理商： GS4900BCNE3
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
75 of 95
Audio_Control
(GS4901B only)
31h
15-10
Reserved. Set these bits to zero when writing to 31h.
–
–
31h
9-7
AFS_Reset_Window - These bits may be used to adjust
the value by which the audio clock counters are allowed
to drift from the output AFS pulse.
The encoding scheme for this register is shown in
Table 3-9
.
NOTE: The default setting of this register will provide a
reset window that is sufficient for most standards. To
maintain correct audio clock frequencies for some
VESA standards, the reset window may have to be
increased from its default setting. In this case, set the
value of this register to 1XX. See
Table 3-9
.
Reference:
Section 3.7.2 on page 53
R/W
010b
31h
6
Reserved. Set this it to zero when writing to 31h.
R/W
0
31h
5
Enable_384fs - set this bit HIGH to enable the 384fs
and 192fs audio clock outputs. This must be set in
addition to registers 3Fh to 41h.
NOTE: If this bit is HIGH, then a 512fs audio clock will
have a 33% duty cycle when fs = 96kHz.
Reference:
Section 3.7.2 on page 53
R/W
0
31h
4-3
Reserved. Set these bits to zero when writing to 31h.
–
–
31h
2
Host_ASR_SEL - set this bit HIGH to select the audio
sample rate using register 32h instead of the external
ASR_SEL[2:0] pins.
The external ASR_SEL[2:0] pins will be ignored, but
should not be left floating.
Reference:
Section 3.7.2 on page 53
R/W
0
31h
1
AFS_F_Pulse - set this bit to 1 to stretch the AFS pulse
duration from 1 line to 1 field.
Reference:
Section 3.8.2 on page 58
R/W
0
31h
0
AFS_Reset_Disable - set this bit HIGH to disable the
10FID input reference pin from resetting the output AFS
pulse. If this bit is set HIGH, the output AFS pulse will
free-run or may be reset using register 1Ah. The
external 10FID pin should not be left floating.
Reference:
Section 3.8.2 on page 58
R/W
0
ASR_SEL[2:0]
(GS4901B only)
32h
15-3
Reserved. Set these bits to zero when writing to 32h.
–
–
32h
2-0
Replaces the external ASR_SEL[2:0] pins when
Host_ASR_Select (bit 2 of address 31h) is HIGH.
The default setting of this register corresponds to an
audio sample rate of 48kHz.
Reference:
Section 3.7.2 on page 53
R/W
011b
RSVD
33h - 38h
–
Reserved.
–
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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