參數(shù)資料
型號(hào)： GS4900BCNE3
廠商： Gennum Corporation
英文描述： SD Clock and Timing Generator with GENLOCK
中文描述： 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 17/95頁(yè)
文件大?。?/td> 898K
代理商： GS4900BCNE3
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
17 of 95
51
PCLK1
–
Output
CLOCK SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Video clock output signal.
PCLK1 presents a video sample rate clock output to the application
layer.
By default, after system reset, the PCLK1 output pin will operate at the
fundamental frequency determined by the setting of the VID_STD[5:0]
pins. It is possible to define other non-standard fundamental clock rates
using the host interface.
It is also possible to select different division ratios for the PCLK1 output
by programming designated registers in the host interface. A clock
output of the fundamental rate, fundamental rate ÷2, or fundamental rate
÷4 may be selected.
By setting designated registers in the host interface, the current drive
capability of this pin may be set high or low. By default, the current drive
will be low.
The PCLK1 output will be held LOW when VID_STD[5:0] = 00h.
52
PCLK1&2_GND
–
Power
Supply
Ground connection for PCLK1&2 circuitry. Connect to GND.
53
PCLK1&2_VDD
–
Power
Supply
Most positive power supply connection for PCLK1&2 circuitry. Connect to
+1.8V DC.
54
PhS_VDD
–
Power
Supply
Most positive power supply connection for the video clock phase shift
internal block. Connect to +1.8V DC.
55
PhS_GND
–
Power
Supply
Ground connection for the video clock phase shift internal block. Connect
to GND.
56
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI
are configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI
are configured as GSPI pins for normal host interface operation.
57
SCLK_TCLK
Non
Synchronous
Input
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
All JTAG / Host Interface address and data are shifted into/out of the
device synchronously with this clock.
Host Mode (JTAG/HOST = LOW):
SCLK_TCLK operates as the host interface serial data clock, SCLK.
JTAG Test Mode (JTAG/HOST = HIGH):
SCLK_TCLK operates as the JTAG test clock, TCLK.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS4901B 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK
GS4901B_09 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK
GS4901BCNE3 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
GS4910B 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK
GS4910BCNE3 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
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