參數(shù)資料
型號: GS4900BCNE3
廠商: Gennum Corporation
英文描述: SD Clock and Timing Generator with GENLOCK
中文描述: 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁數(shù): 44/95頁
文件大小: 898K
代理商: GS4900BCNE3
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
44 of 95
3.5.3 Behaviour on Loss and Re-acquisition of the Reference Signal
By default, the GS4901B/GS4900B will ignore one missing H pulse on the HSYNC
pin and will continue to operate in Genlock mode (although the LOCK_LOST pin
will temporarily be set HIGH). This behaviour is controlled by the Run_Window bits
of register address 24h.
If there are two consecutive missing H pulses on the HSYNC input pin, the
REF_LOST and LOCK_LOST pins will both go HIGH and the device will enter
Freeze mode. An internal flywheel ensures the selected output clock and timing
signals maintain their previous phase and frequency and continue to operate
without glitches.
The VSYNC and FSYNC signals are not monitored in Genlock mode; loss of signal
on these pins will not affect the operation of the device.
NOTE 1: If the input reference is removed and re-applied, all line-based timing
outputs will be inaccurate for up to one frame for all output standards.
Table 3-2: Ambiguous Standard Identification
Number
Standard
H
(27MHz
Clocks)
16_H
(27MHz
Clocks)
V (lines)
F (lines)
Amb_Std_Sel[10:0]
1
1920x1080/60/2:1 interlace (25)
800
12800
562.5
1125
X X X X X X X X X 0 0
1920x1080/30/PsF (30)
800
12800
562.5
1125
X X X X X X X X X 0 1
1920x1035/60/2:1 interlace (19)
800
12800
562.5
1125
X X X X X X X X X 1 0
2
1920x1080/59.94/2:1 interlace (26)
800.8
12813
562.5
1125
X X X X X X X 0 0 X X
1920x1080/29.97/PsF (32)
800.8
12813
562.5
1125
X X X X X X X 0 1 X X
1920x1035/59.94/2:1 interlace (20)
800.8
12813
562.5
1125
X X X X X X X 1 0 X X
3
1920x1080/50/2:1 interlace (27)
960
15360
562.4
1125
X X X X X 0 0 X X X X
1920x1080/25/PsF (34)
960
15360
562.4
1125
X X X X X 0 1 X X X X
4
601 525 / 2:1 interlace (3)
1716
27456
262.5
525
X X X 0 0 X X X X X X
720x486/59.94/2:1 interlace (7)
1716
27456
262.5
525
X X X 0 1 X X X X X X
4fsc 525 / 2:1 interlace (1)
1716
27456
262.5
525
X X X 1 0 X X X X X X
601 - 18MHz 525/2:1 interlace (5)
1716
27456
262.5
525
X X X 1 1 X X X X X X
5
601 625 / 2:1 interlace (4)
1728
27648
312.5
625
X 0 0 X X X X X X X X
720x576/50/2:1 interlace (8)
1728
27648
312.5
625
X 0 1 X X X X X X X X
Composite PAL 625/2:1/25 (2)
1728
27648
312.5
625
X 1 0 X X X X X X X X
601 - 18MHz 625/2:1 interlace (6)
1728
27648
312.5
625
X 1 1 X X X X X X X X
6
RSVD
RSVD
RSVD
RSVD
RSVD
0 X X X X X X X X X X
720x483/59.94/1:1 progressive (9)
858
13728
525
525
1 X X X X X X X X X X
‘X’ signifies ‘don’t care.’ The X bit will be ignored when determining which standard to select in each of the 6 groups above.
NOTE: When the SD input reference format of 720x483/59.94/1:1 (VID_STD = 9) is applied to the input, the user must set bit [15] of the of the
Amb_Std_Sel register address to '1' before the device will recognize this reference.
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