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參數(shù)資料
| 型號： | GS4900BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 67/95頁 |
| 文件大?。?/td> | 898K |
| 代理商： | GS4900BCNE3 |
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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
67 of 95
Input_Standard
0Fh
15-13
Reserved. Set these bits to zero when writing to 0Fh.
–
–
0Fh
12
Force_Input - Set this bit HIGH to force the
GS4901B/GS4900B to recognize the applied input
reference format as the standard programmed in bits
11-6 of this register.
R/W
0
0Fh
11-6
Forced_Standard - When bit 12 is set HIGH, the
GS4901B/GS4900B will use the value programmed in
these bits, rather than the value in bits 5-0, to determine
the input reference format. The 6-bit value programmed
here should always correspond to the VID_STD[5:0]
value of the applied reference.
These bits should not be programmed for normal
operation.
R/W
0
0Fh
5-0
Detected_Standard - Contains the video standard
applied to the input reference pins once it has been
detected. These bits are set by the Reference Format
Detector block and correspond to the VID_STD[5:0]
value of the standard as listed in
Table 1-2
.
The Detected_Standard bits will be set to zero if no input
reference signal is applied or if the input reference
signal is not an automatically recognized video format.
Otherwise the value will be between 1 and 54.
Reference:
Section 3.5.2 on page 43
R/W
N/A
Amb_Std_Sel
10h
15-11
Reserved. Set these bits to zero when writing to 10h.
–
–
10h
10-0
The user may set this register to distinguish between
different formats that look identical to the internal
Reference Format Detector block. See
Table 3-2
.
Reference:
Section 3.5.2.1 on page 43
R/W
0
Reference_Standard_Disable
13h-11h
38-0
The Reference_Standard_Disable register may be used
to disable/enable one or more of the input standards
given in
Table 1-2
from being recognized by the device
and used to genlock the output. This is done by setting
the bit HIGH that corresponds to the VID_STD[5:0]
value of the video format.
For example, if bit 5 is set HIGH, then the output clock
and timing signals will not genlock to an input reference
with timing corresponding to VID_STD[5:0] = 5 in
Table 1-2
.
Likewise, to enable recognition of VID_STD[5:0] = 26
(1080i/59.94) as an input reference format, the user
must set bit 26 LOW.
Address 13h = bits 38-32*
Address 12h = bits 31-16
Address 11h = bits 15-0
*Bits 47-39 of address 13h should always be written
HIGH.
Reference:
Section 3.5 on page 42
R/W
FFFFh
FFFFh
F800h
RSVD
14h
–
Reserved
–
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS4901B | SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4910B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4901B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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