參數(shù)資料
型號: GS4900BCNE3
廠商: Gennum Corporation
英文描述: SD Clock and Timing Generator with GENLOCK
中文描述: 統(tǒng)計時鐘和定時發(fā)生器鎖相
文件頁數(shù): 49/95頁
文件大?。?/td> 898K
代理商: GS4900BCNE3
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
49 of 95
For example, to program a loop bandwidth of 25Hz given a 54MHz video clock and
a reference with a 27MHz video clock and 1716 clocks per line, the following steps
are necessary:
1. Calculate H_Feedback_Divide:
Therefore, H_Feedback_Divide = 1716.
2. Calculate the value for Video_Res_Genlock:
3. Calculate the value for Video_Cap_Genlock:
Therefore, program Video_Res_Genlock = 37 and Video_Cap_Genlock = 16.
NOTE: The value programmed in the Video_Res_Genlock register must be
between 32 and 42. The value programmed in the Video_Cap_Genlock register
must be greater than 10. These limits define the exact range of loop bandwidth
adjustment available.
3.6.2.2 Loop Bandwidth of the Audio PLL (GS4901B only)
The capacitive component of the filter controlling the audio loop bandwidth is
determined by the Audio_Cap_Genlock register and the resistive component is
determined by the Audio_Res_Genlock register. These two registers are located
at addresses 39h and 3Ah, respectively, of the host interface.
H_Reference_Divide
H_Feedback_Divide
f
f
Hrefin
-----------------
×
f
pclkout
27
MHz
=
f
Hrefin
1716
---27
MHz
=
H_Reference_Divide
H_Feedback_Divide
27
27
1716
×
1
1716
=
=
Video_Res_Genlock
47
log
2
6
25
3
10
9
×
(
)
×
×
1716
×
(
)
+
37
=
=
Video_Cap_Genlock
37
21
16
=
=
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