
GS1531 Data Sheet
30573 - 4
July 2005
15 of 49
Parallel Input
Parallel Clock Frequency
f
PCLK
–
13.5
–
148.5
MHz
4
–
Parallel Clock Duty Cycle
DC
PCLK
–
40
–
60
%
6
–
Input Data Setup Time
t
su
–
2.0
–
–
ns
5
–
Input Data Hold Time
t
ih
–
1.5
–
–
ns
5
–
Serial Digital Output
Serial Output Data Rate
DR
SDO
–
–
1.485
–
Gb/s
1
–
–
–
1.485/1.001
–
Gb/s
9
–
–
–
270
–
Mb/s
1
–
Serial Output Swing
Δ
V
SDD
RSET = 281
Ω
75
Ω
load
650
800
950
mVp-p
1
–
Serial Output Rise Time
20% ~ 80%
tr
SDO
HD signal
–
–
260
ps
1
–
tr
SDO
SD signal
400
550
1500
ps
1
–
Serial Output Fall Time
20% ~ 80%
tf
SDO
HD signal
–
–
260
ps
1
–
tf
SDO
SD signal
400
550
1500
ps
1
–
Serial Output Intrinsic Jitter
t
IJ
Pseudorandom and
pathological HD signal
–
90
125
ps
5
–
t
IJ
Pseudorandom and
pathological SD signal
–
270
350
ps
5
–
GSPI
GSPI Input Clock Frequency
f
SCLK
–
–
–
6.6
MHz
8
–
GSPI Input Clock Duty Cycle
DC
SCLK
–
40
–
60
%
8
–
GSPI Input Data Setup Time
–
–
0
–
–
ns
8
–
GSPI Input Data Hold Time
–
–
1.43
–
–
ns
8
–
GSPI Output Data Hold Time
–
–
2.1
–
–
ns
8
–
GSPI Output Data Delay
Time
–
–
–
–
7.27
ns
8
–
TEST LEVELS
1. Production test at room temperature and nominal supply voltage
with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage
with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of
similar product.
9. Indirect test.
NOTES
1. See
Device Power Up on page 44
,
Figure 4-12
.
Table 2-2: AC Electrical Characteristics (Continued)
T
A
= 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes