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參數(shù)資料
| 型號： | GS1531-CBE2 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1531 HD-LINX-TM II Multi-Rate Serializer |
| 中文描述： | GS1531的HD - LINX進(jìn)程，商標(biāo)第二多速率串行器 |
| 文件頁數(shù)： | 12/49頁 |
| 文件大小： | 500K |
| 代理商： | GS1531-CBE2 |
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GS1531 Data Sheet
30573 - 4
July 2005
12 of 49
J7
V
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking when DETECT_TRS is set LOW. The device will set the
V bit in all outgoing TRS signals for the entire period that the V input signal
is HIGH (IOPROC_EN/DIS must also be HIGH).
The V signal should be set HIGH for the entire vertical blanking period and
should be set LOW for all lines outside of the vertical blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
K1
RSET
Analog
Input
Used to set the serial digital output signal amplitude. Connect to CD_VDD
through 281
Ω
+/- 1% for 800mV
p-p
single-ended output swing.
K2
CD_VDD
–
Power
Power supply connection for the serial digital cable driver. Connect to
+1.8V DC analog.
K3, K4
SDO, SDO
Analog
Output
Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or
270Mb/s.
The slew rate of these outputs is automatically controlled to meet SMPTE
292M and 259M requirements according to the setting of the SD/HD pin.
K5
CD_GND
–
Power
Ground connection for the serial digital cable driver. Connect to analog
GND.
K6
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured as GSPI pins for normal host interface operation.
K7
F
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS
signals for the entire period that the F input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2 and should
be set LOW for all lines in field 1 and for all lines in progressive scan
systems.
The F signal is ignored when DETECT_TRS = HIGH.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1532 | HD-LINX II Voltage Controlled Oscillator |
| GS1560 | HD-LINX II Voltage Controlled Oscillator |
| GS9060 | HD-LINX II Voltage Controlled Oscillator |
| GS9062 | HD-LINX II Voltage Controlled Oscillator |
| GS1560ACF | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1531CBE3 | 制造商:Gennum Corporation 功能描述:SERIALISER HD/SD/ASI W/DRIVER 100BGA |
| GS1532 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate Serializer with ClockCleaner |
| GS1532_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate Serializer with ClockCleaner |
| GS1532-CF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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