參數(shù)資料
型號(hào)： GS1531-CBE2
廠商： Gennum Corporation
英文描述： GS1531 HD-LINX-TM II Multi-Rate Serializer
中文描述： GS1531的HD - LINX進(jìn)程，商標(biāo)第二多速率串行器
文件頁(yè)數(shù)： 11/49頁(yè)
文件大?。?/td> 500K
代理商： GS1531-CBE2
GS1531 Data Sheet
30573 - 4
July 2005
11 of 49
H6
SDOUT_TDO
Synchronous
with
SCLK_TCK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW)
SDOUT_TDO operates as the host interface serial output, SDOUT, used
to read status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDOUT_TDO operates as the JTAG test data output, TDO.
H8
H
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data
when DETECT_TRS is set LOW. The device will set the H bit in all
outgoing TRS signals for the entire period that the H input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register, accessible via the host interface.
Active Line Blanking (H_CONFIG = 0
h
)
The H signal should be set HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1
h
)
The H signal should be set HIGH for the entire horizontal blanking period
as indicated by the H bit in the received TRS ID words, and LOW
otherwise.
J5
SDO_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
J6
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data In / Test Data Input
Host Mode (JTAG/HOST = LOW)
SDIN_TDI operates as the host interface serial input, SDIN, used to write
address and configuration information to the internal registers of the
device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDIN_TDI operates as the JTAG test data input, TDI.
NOTE: If the host interface is not being used, tie this pin HIGH.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1531CBE3 制造商:Gennum Corporation 功能描述:SERIALISER HD/SD/ASI W/DRIVER 100BGA
GS1532 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate Serializer with ClockCleaner
GS1532_07 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate Serializer with ClockCleaner
GS1532-CF 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
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