
GL9714 PCI Express
TM
PIPE x4 PHY
2004-2007 Genesys Logic Inc. - All rights reserved.
Page 6
LIST OF FIGURES
F
IGURE
3.1
-
233
P
IN
LFBGA
P
INOUT
D
IAGRAM
............................................................10
F
IGURE
4.1
–
SMB
US
T
OPOLOGY OF
GL9714..................................................................22
F
IGURE
4.2
–
D
ATA
V
ALIDITY
...........................................................................................22
F
IGURE
4.3
–
START
AND
STOP
C
ONDITION
..................................................................23
F
IGURE
4.4
–
ACK
AND
NACK
S
IGNALING OF
SMB
US
...................................................23
F
IGURE
4.5
–
SMB
US
P
ACKET
P
ROTOCOL
D
IAGRAM
E
LEMENT
K
EY
.............................24
F
IGURE
4.6
–
W
RITE
B
YTE
P
ROTOCOL
.............................................................................24
F
IGURE
4.7
–
R
EAD
B
YTE
P
ROTOCOL
...............................................................................24
F
IGURE
4.8
–
T
HE
M
INIMUM
W
AIT
T
IME FROM
P
OWER ON TO
P
ROGRAMMING
R
EGISTERS
.........................................................................................................................25
F
IGURE
5.1
-
S
IMPLIFIED
D
IAGRAM
..................................................................................26
F
IGURE
5.2
-
T
RANSMITTER
D
ATA
P
ATH PER
L
ANE
.........................................................27
F
IGURE
5.3
-
R
ECEIVER
D
ATA
P
ATH PER
L
ANE
...............................................................28
F
IGURE
8.1
–
D
EFINITION OF
I
NPUT
S
ETUP AND
H
OLD
T
IME
..........................................41
F
IGURE
8.2
–
D
EFINITION OF
O
UTPUT
T
IMING
.................................................................42
F
IGURE
9.1
-
GL9714
233
P
IN
LFBGA
P
ACKAGE
...........................................................45