
GL9714 PCI Express
TM
PIPE x4 PHY
2004-2007 Genesys Logic Inc. - All rights reserved.
Page 20
Offset 02h – LPBKTEST …………………………………………..…………. Default value = 8’h00
BIST0
BIST1
BIST2
--
BCN19
BCN18
BCN17
BCN16
R/W
R/W
R/W
--
R/W
R/W
R/W
R/W
7-5 BIST[0:2]
Select of built-in test pattern
Bit Pattern
00x BIST disabled
100 0000000000 0000000000
010 1111111111
110 0101010101
101 0011111010
1100000101
011 0011111010
1100000101
111 PRBS pattern
1111111111
0101010101
1010101010
0101010101
1010
0
*
01010
0101
1
*
10101
It should be noted that the expected pattern while BIST[0:2]=011 is the same as
BIST[0:2]=101. But when coming out of the transmitter, the two bits with “
*
” in
BIST[0:2]=011 are different from BIST[0:2]=101. As a result, even when there is
no bit error, there will be bit errors intentionally introduced to verify the BIST
circuit is functional.
4 RESERVED
-
3-0 BCN[19:16]
Data pattern for beacon and
TXTEST
Offset 03h – BCNPAT2 ………………………………………………….……. Default value = 8’h03
BCN15
BCN14
BCN13
BCN12
BCN11
BCN10
BCN9
BCN8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 BCN[15:8]
Data pattern for beacon and
TXTEST
Offset 04h – BCNPAT3 ………………………………………………….……. Default value = 8’hFF
BCN7
BCN6
BCN5
BCN4
BCN3
BCN2
BCN1
BCN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 BCN[7:0]
Data pattern for beacon and
TXTEST
Offset 0Ch – BT ……………...…………………………………………...……. Default value = 8’h00
--
--
DDR
--
TXTEST
--
SKPDEL
SKPADD
--
--
R/W
--
R/W
--
R/W
R/W
7-6 RESERVED
-
5 DDR
Enable DDR at PIPE interface and make PCLK = 125MHz @ 8/10-bit mode
3 TXTEST
Enable transmitter test with data pattern BCN[19:0], which are programmed in
REG02h, 03h and 04h
1 SKPDEL
Enable SKP deleting test of SKP ordered sets
0 SKPADD
Enable SKP adding test of SKP ordered sets