參數(shù)資料
型號: GL9714
廠商: Genesys Logic, Inc.
英文描述: PCI ExpressTM PIPE x4 PHY
中文描述: 管x4的PCI ExpressTM物理層
文件頁數(shù): 37/46頁
文件大?。?/td> 527K
代理商: GL9714
GL9714 PCI Express
TM
PIPE x4 PHY
2004-2007 Genesys Logic Inc. - All rights reserved.
Page 37
7.4 Power Consumption
Power Consumption with 2-Lanes and 4-Lanes Operation
Table 7.4 – Typical Power Consumption with 2-Lanes, 4-Lanes, and 1.2V Differential Peak to
Peak Output Voltage
Current at
2.5V (mA)
Current at
Analogue
1.8V (mA)
Current at
Digital 1.8V
(mA)
Current at
Reference Voltage
1.25V (mA)
Operation
Condition
Power
State
Operation Mode
Power
Consumption
(mW)
184
285
128
0
All on
P0
8-bit @250MHz
PCLK, 4-Lanes
1203.4
14
207
89
0
PLL on
TX idle
RX on
P0s
8-bit @250MHz
PCLK, 4-Lanes
567.8
14
174
48
0
PLL on
TX idle
RX idle
P1
8-bit @250MHz
PCLK, 4-Lanes
434.6
9
146
10
0
PLL off
TX idle
RX idle
P2
8-bit @3.13MHz
PCLK, 4-Lanes
303.3
107
161
81
0
All on
P0
16-bit @125MHz
PCLK, 2-Lanes
703.1
17
117
65
0
PLL on
TX idle
RX on
P0s
16-bit @125MHz
PCLK, 2-Lanes
370.1
17
101
45
0
PLL on
TX idle
RX idle
P1
16-bit @125MHz
PCLK, 2-Lanes
305.3
9
74
9
0
PLL off
TX idle
RX idle
P2
16-bit @1.56MHz
PCLK, 2-Lanes
171.9
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