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參數(shù)資料
| 型號： | GL9714 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM PIPE x4 PHY |
| 中文描述： | 管x4的PCI ExpressTM物理層 |
| 文件頁數(shù)： | 32/46頁 |
| 文件大?。?/td> | 527K |
| 代理商： | GL9714 |
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GL9714 PCI Express
TM
PIPE x4 PHY
2004-2007 Genesys Logic Inc. - All rights reserved.
Page 32
6.10 Operation Mode and Multi-Functional Pins
There are four modes for GL9714 operation which is selected by pin OPMODE[1:0].
Mode
[1]
[0]
Description
1
0
0
4 lanes, 8 bit mode
2
0
1
2 lanes, 16 bit mode
3
1
0
4 lanes, 10 bit mode
4
1
1
For scan test only
Mode 1
:
The GL9714 is configured into an x4 lane, 8-bit parallel bus and acts as a 4-lane PCI Express PHY.
The parallel bus is synchronous with PCLK at 250 MHz. By transitioning both TXCMPx and
TXIDLEx to high for individual lane, the GL9714 in this mode is able to behave as an x1 or x2 PHY.
Mode 2
: The GL9714 acts as a 2-lane PHY with a 16-bit parallel interface at 125 MHz. In this mode, only
lane B and lane C are activated. Again, by disabling either lane using TXCMPx and TXIDLEx,
the GL9714 can be configured into an x1 PHY with16-bit parallel bus.
Mode 3
: The GL9714 is configured as a quad SerDes with 10-bit parallel bus.
Mode 4
: For scan test only
Table 6.1 - Pin Functions
Pin Number
Mode 1
Mode 2
Mode 3
T14
PCLK(O)
PCLK(O)
TBC(O)
C17
TXDA7(I)
TXDB15(I)
TDA7(I)
C16
TXDA6(I)
TXDB14(I)
TDA6(I)
E14
TXDA5(I)
TXDB13(I)
TDA5(I)
D15
TXDA4(I)
TXDB12(I)
TDA4(I)
D14
TXDA3(I)
TXDB11(I)
TDA3(I)
E16
TXDA2(I)
TXDB10(I)
TDA2(I)
C14
TXDA1(I)
TXDB9(I)
TDA1(I)
D13
TXDA0(I)
TXDB8(I)
TDA0(I)
N16
TXDB7(I)
TXDB7(I)
TDB7(I)
L15
TXDB6(I)
TXDB6(I)
TDB6(I)
N17
TXDB5(I)
TXDB5(I)
TDB5(I)
M15
TXDB4(I)
TXDB4(I)
TDB4(I)
M16
TXDB3(I)
TXDB3(I)
TDB3(I)
K14
TXDB2(I)
TXDB2(I)
TDB2(I)
L16
TXDB1(I)
TXDB1(I)
TDB1(I)
L17
TXDB0(I)
TXDB0(I)
TDB0(I)
R4
TXDC7(I)
TXDC15(I)
TDC7(I)
T3
TXDC6(I)
TXDC14(I)
TDC6(I)
R5
TXDC5(I)
TXDC13(I)
TDC5(I)
U2
TXDC4(I)
TXDC12(I)
TDC4(I)
P6
TXDC3(I)
TXDC11(I)
TDC3(I)
T4
TXDC2(I)
TXDC10(I)
TDC2(I)
R6
TXDC1(I)
TXDC9(I)
TDC1(I)
U4
TXDC0(I)
TXDC8(I)
TDC0(I)
H3
TXDD7(I)
TXDC7(I)
TDD7(I)
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