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參數(shù)資料
| 型號： | GL9714 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM PIPE x4 PHY |
| 中文描述： | 管x4的PCI ExpressTM物理層 |
| 文件頁數(shù)： | 39/46頁 |
| 文件大小： | 527K |
| 代理商： | GL9714 |
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GL9714 PCI Express
TM
PIPE x4 PHY
2004-2007 Genesys Logic Inc. - All rights reserved.
Page 39
7.5 Differential Transmitter and Receiver Serial Output
Transmitter Serial Output
Table 7.6 – Transmitter Serial Output
Symbol
Parameter
Min
Typ
Max
Unit
UI
Unit interval
399.88
400
400.12
ps
V
TX-DIFFp-p
Differential peak to peak output voltage
0.8
-
1.2
V
V
TX-DE-RATIO
De-emphasized
voltage (Ratio)
differential
output
-3.0
-3.5
-4.0
dB
T
TX-EYE
Minimum TX eye width
0.7
-
-
UI
T
TX-EYE-MEDIAN-to-MAX-JITTER
Maximum time between the jitter
median and maximum deviation from
the median
-
-
0.15
UI
T
TX-RISE
,
T
TX-FALL
D+/D- TX output rise/fall time
0.125
-
-
UI
V
TX-CM-ACp
RMS AC peak common mode output
voltage
-
-
20
mV
V
TX-CM-DC-ACTIVE-IDLE-DELTA
Absolute delta of DC common mode
voltage during L0 and electrical idle
Absolute delta of DC common mode
voltage between D+ and D-
Electrical idle differential peak output
voltage
The amount of voltage change allowed
during receiver detection
0
-
100
mV
V
TX-CM-DC-LINE-DELTA
0
-
25
mV
V
TX-IDLE-DIFFp
0
-
20
mV
V
TX-RCV-DETECT
-
-
600
mV
V
TX-DC-CM
The TX DC common mode voltage
0
-
3.6
V
I
TX-SHORT
TX short circuit current limit
-
-
90
mA
T
TX-IDLE-MIN
Minimum time spent in electrical idle
50
-
-
UI
T
TX-IDLE-SET-TO-IDLE
Maximum time to transition to a valid
electrical idle after sending an electrical
idle ordered set
Maximum time to transition to valid TX
specifications after leaving an electrical
idle condition
-
-
20
UI
T
TX-IDLE-TO-DIFF-DATA
-
-
20
UI
RL
TX-DIFF
Differential return loss
12
-
-
dB
RL
TX-CM
Common mode return loss
6
-
-
dB
Z
TX-DIFF-DC
DC differential TX impedance
80
100
120
Ω
L
TX-SKEW
Lane-to-lane output skew
-
-
500 + 2UI
ps
C
TX
AC coupling capacitor
75
-
200
nF
Tcrosslink
Crosslink random timeout
0
-
1
ms
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