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參數(shù)資料
| 型號： | GL9711-TGGXX |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM PIPE x1 PHY |
| 中文描述： | 的PCI ExpressTM管x1物理層 |
| 文件頁數(shù)： | 8/42頁 |
| 文件大小： | 423K |
| 代理商： | GL9711-TGGXX |
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GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 8
CHAPTER 1 GENERAL DESCRIPTION
The GL9711 is a 1-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base
Specification rev. 1.0a and Intel
’
s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates one
SerDes and the Physical Coding Sublayer (PCS) which performs 8b/10b encoding and decoding, elastic buffer
and receiver detection, data serialization and deserialization. The SerDes in the GL9711 supports an effective
serial interface speed (2.5 Gb/s) of data bandwidth, intended for use in ultrahigh-speed bi-directional data
transmission system. The GL9711 can also be externally configured for various parallel bus width which is
flexible and suitable for implementation. It also supports four operational states for power management to
minimize power consumption. For production and self-test purposes, the GL9711 provides BIST and an internal
loopback capability.
The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband
data transmission over an on-chip termination resister of 50 Ohm +/- 10%.
This device can also be used to replace parallel data transmission architectures by providing a reduction in the
number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered
to the receiver over a serial channel. It is then reconstructed into its original parallel format. The maximum data
transfer rate in each direction is 256M bytes per second. It also offers various power saving modes to
significantly reduce power consumption as well as scalability for a higher data rate in the future.
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