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參數(shù)資料
| 型號(hào)： | GL9711-TGGXX |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM PIPE x1 PHY |
| 中文描述： | 的PCI ExpressTM管x1物理層 |
| 文件頁(yè)數(shù)： | 17/42頁(yè) |
| 文件大小： | 423K |
| 代理商： | GL9711-TGGXX |
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GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 17
VSSGR
C15
P
Ground for the guard ring of the SerDes block
Serial Signals
Pin Name
Pin#
Type
Description
RXN
A12
I
Received serial input, complement
RXP
B12
I
Received serial input, true
Connects an external 5.1K
resistor to ground for calibrating the
on-chip termination resistors
Transmitted serial output, complement
RTERM
D8
I
TXN
A10
O
TXP
B10
O
Transmitted serial output, true
Other Signals
Pin Name
I/O
Standard
Analogue
Pin#
Type
Description
REFCLKP
A1
I
Reference clock signal
REFCLKN
Analogue
B1
I
Reference clock signal
Connect to 25MHz crystal when using
crystal as the reference clock source
Connect to 25MHz crystal/oscillator
when using crystal/oscillator as the
reference clock source
Test clock/SMBus clock
OSC25MO
Crystal
C1
O
OSC25MI
Crystal/
Oscillator
D1
I
TESTC/SMC LVCMOS2
U11
I
TESTD/SMD LVCMOS2
T10
I/O Test data/SMBus data
Configures clock input source
When SCC=1, the chip clock sources from a
pair of differential signals, REFCLKP and
REFCLKN, with a nominal frequency of 100
MHz.
When SCC=0, the chip clock sources from a
crystal at 25MHz.
Operational Mode of the GL9711
00 8-bit mode
01 16-bit mode
10 10-bit mode
11 Internal use only
SCC
LVCMOS2
R10
I
OPMODE[1:0]
LVCMOS2
U10, R9
I
NC
-
A2, A4, A6, A8,
A14, A16, B2, B4,
B6, B8, B14, B16,
C2, C3, C5, C6,
C9, C11, C13, D3,
D6, D10, D11,
D12, D17, E1, E2,
E3, E4, F2, F3, F4,
F14, F15, G1, G3,
G4, G14, H1, H2,
H3, H4, J1, J3, J4,
K2, K3, K17, L3,
-
No connection
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