參數(shù)資料
型號(hào): GL9711-TGGXX
廠商: Genesys Logic, Inc.
英文描述: PCI ExpressTM PIPE x1 PHY
中文描述: 的PCI ExpressTM管x1物理層
文件頁(yè)數(shù): 28/42頁(yè)
文件大?。?/td> 423K
代理商: GL9711-TGGXX
GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 28
5.3 Receiver Data Path Per Lane
Differential Recieiver
Data Recovery Circuit
(DRC)
Serial to Paralle
Elastic Buffer
Loopback path to transmitter
RXN
RXP
RXIDLE
Clock Recovery Circuit
2.5 GHz
K28.5 Detection
RXVLD
RXPLR
Receiver
Status
RXSTS
x10
x10
8b 10b Decoder
x8
Optional 8, 16-bit
Data
x16 or x8
RXDK
Recovered Symbol Clock
Buffer Overflow/Underflow
SKP Added/Removed
Decode Error
Disparity
Error
250 MHz
PCL
Figure 5.3 - Receiver Data Path per Lane
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