參數(shù)資料
型號(hào)： GL9711-TGGXX
廠商： Genesys Logic, Inc.
英文描述： PCI ExpressTM PIPE x1 PHY
中文描述： 的PCI ExpressTM管x1物理層
文件頁數(shù)： 24/42頁
文件大小： 423K
代理商： GL9711-TGGXX
GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 24
Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an acknowledge bit. Bytes
are transferred with the most significant bit (MSB) first. Fig. 4.4 illustrates the positioning of acknowledge
(ACK) and not acknowledge (NACK) pulses relative to other data.
Figure 4.4
–
ACK and NACK Signaling of SMBus
Below is a key to the protocol diagrams.
`
S
Sr
Rd
Wr
x
A
Start Condition
Repeated Start Condition
Read (bit value of 1)
Write (bit value of 0)
Shown under a field indicates that that
field is required to have the value of
‘
x
’
Acknowledge (this bit position may be
‘
0
’
for an ACK or
‘
1
’
for a NACK)
Stop Condition
Master-to-GL9711
GL9711-to-Master
P
Figure 4.5
–
SMBus Packet Protocol Diagram Element Key
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