
GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 30
l
8B/10B Decode Error
When the GL9711 decodes the received 10-bit symbol and detects an error code which does not
correspond to any valid data, it will replace the code with an EDB symbol, assert PHYSTS and encode
RXSTS[2:0] with the values of decode error status, 3
’
b100.
l
Elastic Buffer Overrun and Underrun
When the overrun or underrun of the elastic buffer occurs, the GL9711 will assert PHYSTS and encode
RXSTS[2:0] with the values of decode error status.
Elastic Buffer
Overrun
Underrun
RXSTS Code
101b
110b
In the case of elastic buffer overrun, the GL9711 drops the symbol. For the elastic buffer underrun, the
GL9711 inserts the EDB symbol. The PHYSTS and RXSTS[2:0] are presented on the MAC interface
during the clock cycle where GL9711 drops or inserts the symbol.
l
Disparity Errors
To report a disparity error detected, the GL9711 asserts PHYSTS and encodes RXSTS[2:0] with the values
of decode error status, 3
’
b111.
6.5 Loopback
The GL9711 supports a Loopback mode to re-transmit its received data. When the MAC sets the GL9711 in P0
state and asserts TXDET/LPBK, the GL9711 enters a Loopback. In Loopback, the GL9711 transmits data from it
received data instead of MAC interface. Meanwhile, it presents the received data on the MAC interface as
normal operation.
When set into Loopback mode and acting as a Loopback slave according to the PCI Express Base Specification
Rev. 1.0a, the GL9711 received data from the Loopback master. If the master intends to end the Loopback, it
sends an electrical idle ordered-set to the GL9711. When the MAC detects the electrical idle ordered-set, it
de-asserts TXDET/LPBK and asserts TXIDLE to instruct the GL9711 to stop Loopback. The MAC should take
care the GL9711 has retransmit at least three bytes of the electrical idle before it makes the GL9711
’
s transmitter
into electrical idle.
6.6 Polarity Inversion
The GL9711 supports lane polarity inversion. While pin RXPLR asserted, the GL9711 inverts its received data
on the MAC interface.
6.7 Setting Negative Disparity
To set the running disparity to negative, the MAC asserts TXCMP for one PCLK cycle that matches with the
data that is to be transmitted where running disparity is negative.