參數(shù)資料
型號(hào): GL9711-TGGXX
廠商: Genesys Logic, Inc.
英文描述: PCI ExpressTM PIPE x1 PHY
中文描述: 的PCI ExpressTM管x1物理層
文件頁數(shù): 39/42頁
文件大?。?/td> 423K
代理商: GL9711-TGGXX
GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 39
Figure 8.2
Definition of Output Timing
Table 8.1
Input Setup, Hold Time and Output Timing for 8-bit SDR Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
CYCLE
PCLK cycle time
3.99
4
4.01
ns
Duty-
H
Duty cycle for PCLK high
35
-
50
%
T
IS
Input setup time
-
-
1
ns
T
IH
Input hold time
1
-
-
ns
T
CO
Clock to output delay
-
2.7
3.2
ns
T
OH
Output hold time
1
2.1
-
ns
Table 8.2
Input Setup, Hold Time and Output Timing for 8-bit DDR Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
CYCLE
PCLK cycle time
7.98
8
8.02
ns
T
IS
Input setup time
-
-
1.4
ns
T
IH
Input hold time
0.5
-
-
ns
T
CO
Clock to output delay
-
1.5
1.6
ns
T
OH
Output hold time
0.8
1
-
ns
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