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參數(shù)資料
| 型號： | GL9711-TGGXX |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM PIPE x1 PHY |
| 中文描述： | 的PCI ExpressTM管x1物理層 |
| 文件頁數(shù)： | 15/42頁 |
| 文件大小： | 423K |
| 代理商： | GL9711-TGGXX |
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GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 15
3.4 Pin Descriptions
Table 3.4 - Pin Descriptions
PIPE Interface
Pin Name
I/O Standard
Pin#
Type
Description
RST_N
LVCMOS2
U12
I
Global reset
Parallel interface clock
All data movement across the parallel
interface is synchronous to this clock.
1. For 8-bit mode:
PCLK operates at 250 MHz and is
applied to synchronize all TXD, RXD
data bus and all commands.
2. For 16-bit mode:
PCLK operates at 125 MHz and is
applied to synchronize all TXD, RXD
data bus and all commands.
3. For 10-bit mode(TBC):
PCLK operates at 250 MHz and is
applied to synchronize the TXD data bus
and all commands.
1. For 8-bit and 16-bit modes:
Encodes receiver status and error codes
for the received data stream and receiver
detection
000 Received data OK
001 1 SKP added
010 1 SKP removed
011 Receiver detected
100 8B/10B decode error
101 Elastic Buffer overflow
110 Elastic Buffer underflow
111 Receiver disparity error
2. For 10-bit modes:
RXSTS[2]: RBC, synchronize the RXD
data bus
RXSTS[1]: RXPRSNT, report the result
of receiver detection
RXSTS[0]: RXD9, bit 9 of RXD data
bus
Indicates receiver detection of an electrical
idle
This is an asynchronous signal.
Used to communicate completion of several
PHY functions including power state
transitions and receiver detection
Indicates symbol lock and valid data on
RXDx and RXDKx
1. For 8-bit and 16-bit modes:
Sets the running disparity to negative
2. For 10-bit mode:
TXD9, bit 9 of TXD data bus
Forces Tx output to electrical idle
PCLK
SSTL2_I
T14
O
RXSTS[2:0]
SSTL2_I
T17, M14, P17
O
RXIDLE
LVCMOS2
T12
O
PHYSTS
SSTL2_I
U5
O
RXVLD
LVCMOS2
P11
O
TXCMP
SSTL2_I
L14
I
TXIDLE
LVCMOS2
R12
I
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