參數(shù)資料
型號: GL843
廠商: Genesys Logic, Inc.
英文描述: High Speed USB 2.0 With ADF 2-in-1 Scanner Controller
中文描述: 高速USB 2.0同盟2合1掃描儀控制器
文件頁數(shù): 49/84頁
文件大小: 837K
代理商: GL843
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 49
7-6 STEPSEL[1:0]
For type selection of table one, table two and table three in scanning mode.
(1) For bipolar motors:
00 Full step (for 1939, 1940, 2916, 6219, 3955, 3967).
01 Half step (for 1939, 1940, 2916, 6219, 3955, 3967).
10 Quarter step (for 2916, 6219, 3955, 3967).
11 Eighth step (for 3955, 3967).
(2) For unipolar motors:
00 Two-phase-on full step.
01 Half step.
10 Reserved.
11 Single-phase-on full step.
5-0
MTRPWM[5:0]
PWM duty cycle selection of table one, table two and table three of motor phase
of unipolar motors in scanning mode.
MTRPWM = 0 1/64 duty
= 1 2/64 duty
= 2 3/64 duty
……
= 63 64/64 duty
Note: If PHFREQ < 0FH,then PWM setting must < (PHFREQ+1)*4
Offset 68h
……
..
……
..
………………
..
………
..
.
………
..
.
..
………
..
. Default value = 8
h7F
FSTPSEL1 FSTPSEL0
FASTPWM5 FASTPWM4 FASTPWM3 FASTPWM2 FASTPWM1 FASTPWM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-6 FSTPSEL[1:0]
For type selection of table four and table five in command mode.
(1) For bipolar motors:
00 Full step (for 1939, 1940, 2916, 6219, 3955, 3967).
01 Half step (for 1939, 1940, 2916, 6219, 3955, 3967).
10 Quarter step (for 2916, 6219, 3955, 3967).
11 Eighth step (for 3955, 3967).
(2) For unipolar motors:
00 Two-phase-on full step.
01 Half step.
10 Reserved.
11 Single-phase-on full step.
5-0
FASTPWM[5:0]
PWM duty cycle selection of table four and table five of motor phase of unipolar
motors in scanning mode.
FASTPWM = 0 1/64 duty
= 1 2/64 duty
= 2 3/64 duty
……
= 63 64/64 duty
Note: If PHFREQ < 0FH,then PWM setting must < (PHFREQ+1)*4
Offset 69h
……
..
………………
..
………
..
………
..
.
………
..
.
..
..
..
. Default value = 8
h00
FSHDEC7 FSHDEC6
FSHDEC5
FSHDEC4
FSHDEC3
FSHDEC2
FSHDEC1
FSHDEC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FSHDEC[7:0]
Deceleration steps after scanning finished (table three).
Note: It cannot be programmed to logic zero.
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